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Observer
Observer
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Registered: ‎07-19-2018

MIO -> EMIO -> MIO workaround?

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I am trying to overcome a MIO hardware conflict... Is it at all possible to route a MIO to EMIO then back to a MIO pin?

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-21-2014

No, it is not.  EMIO can only be used to route PS peripheral pins to/from the PL.  You cannot do the opposite, that is, you can't access MIO pins directly from the PL.  You would have to use a master in the PL to control the PS peripheral - i.e. to use MIO as "GPIO" from the PL, you could read/write to the PS GPIO controller with a PL master. 

Regards,

Terry

 

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Xilinx Employee
Xilinx Employee
615 Views
Registered: ‎01-21-2014

No, it is not.  EMIO can only be used to route PS peripheral pins to/from the PL.  You cannot do the opposite, that is, you can't access MIO pins directly from the PL.  You would have to use a master in the PL to control the PS peripheral - i.e. to use MIO as "GPIO" from the PL, you could read/write to the PS GPIO controller with a PL master. 

Regards,

Terry

 

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