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2,326 Views
Registered: ‎05-10-2010

MPMC+NPI data is written twice to memory

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Hi,

 

I managed to design a custom IP that writes data to DDR2 memory. I'm using MPMC with NPI. The mhs looks like:

 

 

...

BEGIN my_npi
 PARAMETER INSTANCE = my_npi_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE XIL_NPI = my_npi_0_XIL_NPI
 PORT Compare_Error = my_npi_0_Compare_Error
 PORT XIL_NPI_Clk = clk_100_0000MHzPLL0
 PORT XIL_NPI_Rst = Debug_SYS_Rst
 PORT Current_State = my_npi_0_Current_State
 PORT Button = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR2_SDRAM
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_NUM_IDELAYCTRL = 3
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
 PARAMETER C_MEM_PARTNO = mt4htf3264h-53e
 PARAMETER C_MEM_ODT_TYPE = 1
 PARAMETER C_MEM_CLK_WIDTH = 2
 PARAMETER C_MEM_ODT_WIDTH = 2
 PARAMETER C_MEM_CE_WIDTH = 1
 PARAMETER C_MEM_CS_N_WIDTH = 1
 PARAMETER C_MEM_DATA_WIDTH = 64
 PARAMETER C_DDR2_DQSN_ENABLE = 1
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER HW_VER = 6.01.a
 PARAMETER C_PIM1_BASETYPE = 4
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 5000
 PARAMETER C_MPMC_BASEADDR = 0x90000000
 PARAMETER C_MPMC_HIGHADDR = 0x9fffffff
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE MPMC_PIM1 = my_npi_0_XIL_NPI
 PORT MPMC_Clk0 = clk_200_0000MHzPLL0
 PORT MPMC_Clk0_DIV2 = clk_100_0000MHzPLL0
 PORT MPMC_Clk90 = clk_200_0000MHz90PLL0
 PORT MPMC_Clk_200MHz = clk_200_0000MHzPLL0
 PORT MPMC_Rst = sys_periph_reset
 PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk_pin
 PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin
 PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE_pin
 PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n_pin
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
 PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin
 PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin
 PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n_pin
 PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin
 PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr_pin
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
 PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin
END

...

 

Writing to memory works (64bit width data burst write), but the data appers twice in memory.

E.g. if I write the values 0x1, 0x2, 0x3 from my IP to memory, the memory looks like:

address   data

0x0          0x1

0x8          0x1

0x16        0x2

0x24        0x2

0x32        0x3

0x40        0x3

 

What could be the problem here?

Chipscope waveform looks like the timing diagram in the MPMC documentaion.

In Chipscope I see the proper data sequenze beeing pushed to write_fifo, 0x1, 0x2, 0x3 etc.

 

MPMC runs @200Mhz but my_npi core runs @100Mhz. Could this be the problem???

 

Thanks in advance!

 

 

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Accepted Solutions
Highlighted
2,771 Views
Registered: ‎05-10-2010

Ok, problem solved: MPMC and NPI core need to run on same frequency!

View solution in original post

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Highlighted
2,772 Views
Registered: ‎05-10-2010

Ok, problem solved: MPMC and NPI core need to run on same frequency!

View solution in original post

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