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logicaledge
Observer
Observer
1,059 Views
Registered: ‎12-16-2014

MPSoC PS DDR ECC

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Is it possible to enable ECC for the PS DDR controller but have it only apply to a limited range of DDR address space? Thanks.

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pmarise
Xilinx Employee
Xilinx Employee
986 Views
Registered: ‎10-25-2018

Hi There,

ECC is for entire memory, enabling of ECC for limited range of DDR address space is not possible. Becuase ECC is actually for WR and RD operation, does not matter where it is being read from / write to

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pmarise
Xilinx Employee
Xilinx Employee
987 Views
Registered: ‎10-25-2018

Hi There,

ECC is for entire memory, enabling of ECC for limited range of DDR address space is not possible. Becuase ECC is actually for WR and RD operation, does not matter where it is being read from / write to

View solution in original post

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joaragj
Observer
Observer
902 Views
Registered: ‎09-10-2018

Probably a stupid question, but does the DMA also go through the PS ECC ? If not, how can the DMA be used together with the ECC? Is it possible to tempoerly disable the ECC while reading from the DMA memory region?

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joaragj
Observer
Observer
843 Views
Registered: ‎09-10-2018

I also have the same question!  Anyone know? Would also love to have more information about the inner workings of the PS ECC

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pmarise
Xilinx Employee
Xilinx Employee
829 Views
Registered: ‎10-25-2018

Hi,

Yes DMA writes/read also go through ECC