11-02-2016 02:35 AM
I have an application where i need to stream high bandwidth data using PCIe from the MPSoC(Configured as RC or RP) but without using CPU.
Unfortunatly the first MPSoC devices (such as the ES1 on my ZCU102) do not include a PL PCIe block but only the PS PCIe.
Is it theoreticaly possible to have the PL access the PS PCIe through one of the AXI ports (AXI_HP or AXI_HPC) via the Core Switch ?
Can i have the APU setup the PCIe using the normal Linux bringup and then have the PL perform writes to the PCIe registers
I have already reviewed the TRM, Forums, example designs and XAPP1289 but have not found any PL references.
11-02-2016 09:15 AM
11-03-2016 09:40 AM