cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jtstringer_cat
Adventurer
Adventurer
8,932 Views
Registered: ‎03-31-2016

MPSoC bare metal A53 PL to PS Interrupt

Jump to solution

I'm porting a design from the Zynq 7000 series to the MPSoC.  I have one interrupt from the PL that I need to service.  Seems like the interrupt structures have become more complicated and it's not working -- i.e. I can see via ila that the interrupt is going off in hardware but the interrupt service routine is not called.  

 

Given my simple application at the moment (baremetal A53) the PL to PS interrupt I picked in configuring the MPSoC was the APU Legacy Interrupts (IRQ,FIQ).  Then I connected my 1 interrupt to the pl_ps_apugic_fig[0] as shown below.

 

For the code I used what was working in the Zynq 7000.  The only difference was I changed the interrupt id.  What am I doing wrong?

 

#define INTC_INTERRUPT_ID 28 // for PPI FIQ
#define INTC_HANDLER XScuGic_InterruptHandler
#define INTC_DEVICE_ID XPAR_PSU_ACPU_GIC_DEVICE_ID

 

int SetupInterruptSystem(){


   /// Initialize the Interrupt controller driver so that is ready to use
   if(!(IntcConf = XScuGic_LookupConfig(INTC_DEVICE_ID))){ return 1;}

 

   /// Initialize the SCU and GIC, specify edge sensitivity & register callback
   if(XScuGic_CfgInitialize(&Intc,IntcConf,IntcConf->CpuBaseAddress)){ return 1;}

 

   XScuGic_SetPriorityTriggerType(&Intc,INTC_INTERRUPT_ID,0xA0,0x3);

 

   if(XScuGic_Connect(&Intc, INTC_INTERRUPT_ID, //connect interrupt handler
      (Xil_ExceptionHandler) IntCallback, (void *)&Intc)){ return 1;}

 

   XScuGic_Enable(&Intc, INTC_INTERRUPT_ID); // Enable IRQ F2P interrupts

 

   /// Initialize exception table & register interrupt controller handler with it
   Xil_ExceptionInit();
   Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
      (Xil_ExceptionHandler)INTC_HANDLER,&Intc);
   Xil_ExceptionEnable();
   return 0;
}

 

void IntCallback(void *InstancePtr){

   // interrupt service routine

}

 

 

intconfig.PNG

 

mpsocint.PNG

0 Kudos
1 Solution

Accepted Solutions
jtstringer_cat
Adventurer
Adventurer
12,695 Views
Registered: ‎03-31-2016

Good suggestion @muzaffer  I tried that but it still didn't work.  Then I decided to try the regular IRQs and used an interrupt ID of 121 and it worked!  Not sure why the legacy stuff doesn't work.  The other question, is aren't there supposed to be 8 interrupts for IRQ0?  It only lets me do 1.

 

mpsoc good int.PNG

View solution in original post

0 Kudos
6 Replies
muzaffer
Teacher
Teacher
8,923 Views
Registered: ‎03-31-2012

@jtstringer_cat just a quick search shows that even on zynq soc fiq is a little different: https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/How-to-set-up-the-FIQ/td-p/492794 maybe there is an equivalent code for mpsoc?

 

why don't you move your line to irq and see if that gets triggered.

 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
jtstringer_cat
Adventurer
Adventurer
12,696 Views
Registered: ‎03-31-2016

Good suggestion @muzaffer  I tried that but it still didn't work.  Then I decided to try the regular IRQs and used an interrupt ID of 121 and it worked!  Not sure why the legacy stuff doesn't work.  The other question, is aren't there supposed to be 8 interrupts for IRQ0?  It only lets me do 1.

 

mpsoc good int.PNG

View solution in original post

0 Kudos
tetsuo_yamashita
Participant
Participant
7,214 Views
Registered: ‎08-03-2017
@jtstringer_cat I tried the regular IRQs and used an interrupt ID of 121, but it didn't work. I have connected pl_ps_irq0[0] to a push_button via a register. So when I push the button, pl_ps_irq[0] become high. But I can't verify interrupt from PL. If you don't mind, could I see your design and sources on bare metal A53?
Tags (2)
0 Kudos
jtstringer_cat
Adventurer
Adventurer
7,189 Views
Registered: ‎03-31-2016

@tetsuo_yamashita If you have the interrupt hooked up as I do and you can see it go high with an ILA then probably the issue is with the code.  Here's a snippet of my code that sets up the interrupt handler.

 

///Define relevant interrupt controller parameters
#define INTC_INTERRUPT_ID 121  //31u //91 //most significant bit
#define INTC_HANDLER      XScuGic_InterruptHandler
#define INTC_DEVICE_ID    XPAR_PSU_ACPU_GIC_DEVICE_ID // jts 2017/1/3 XPAR_PS7_SCUGIC_0_DEVICE_ID

static XScuGic Intc; 
static XScuGic_Config *IntcConf;



int SetupInterruptSystem(){
  /// Initialize the Interrupt controller driver so that is ready to use 
  if(!(IntcConf = XScuGic_LookupConfig(INTC_DEVICE_ID))){             return 1;}

  /// Initialize the SCU and GIC, specify edge sensitivity & register callback
  if(XScuGic_CfgInitialize(&Intc,IntcConf,IntcConf->CpuBaseAddress)){ return 1;}

  XScuGic_SetPriorityTriggerType(&Intc,INTC_INTERRUPT_ID,0xA0,0x3);

  if(XScuGic_Connect(&Intc, INTC_INTERRUPT_ID, //connect interrupt handler 
	    (Xil_ExceptionHandler) IntCallback, (void *)&Intc)){          return 1;}

  XScuGic_Enable(&Intc, INTC_INTERRUPT_ID);    // Enable IRQ F2P interrupts

  /// Initialize exception table & register interrupt controller handler with it
  Xil_ExceptionInit();
  Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
      (Xil_ExceptionHandler)INTC_HANDLER,&Intc);
  Xil_ExceptionEnable();
  return 0;
}


void IntCallback(void *InstancePtr){

   // interrupt service routine here
}

 

 

 

tetsuo_yamashita
Participant
Participant
7,130 Views
Registered: ‎08-03-2017
@jtstringer_cat Thank you for your reply! I'll check IRQ go high with ILA and interrupt with your code.
0 Kudos
lar_fer
Contributor
Contributor
3,242 Views
Registered: ‎04-25-2017

Hello

 

I know is a very simple question but I have the same issue as described here and the proposed solution is not working for me.

I have a very simple design with axi gpios and axi timer. I read this tutorial to connect PL interrupt to PS and used the code with minor changes.

https://fpga.incomeself.com/tutorial-sending-an-interrupt-from-pl-to-ps-for-xilinx-zynq-ultrascale-mpsoc/

The thing is that the code never jumps to the interrupt handler if I run the code in an A53 core. On the other side, the same exact code running on a R5 core does the work.

Is there something I'm missing?

Regards,

 

blk_ultrazed.png
0 Kudos