Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎06-12-2018

MPU change memory region attribute

Hi there,
I am working with the Zynq UltraScale+ MPSoC XCZU2EG. I figured out that when I want to read data from the RAM or the OCM then this data is cached. In my application I do not want to cache a specific memory region. It works with the use of the function void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib) for the APU with an A53. The attribute I am passing is from xil_mmu.h:

#define NORM_NONCACHE 0x401UL /* Normal Non-cacheable*/

So far so good.

Now I want to achieve the same for the RPU with a R5. I know that there is no MMU on the RPU, but there is a MPU. If I disable the MPU region for the OCM then the OCM data won't be cached anymore. If I disable the MPU region for the ram the program stops working at the line of code.

With that getting stuck there, I had another idea: changeing the attributes of a memory region. I think that is actually a better way to deal with this problem but I got stuck there, too. When I use the function

Xil_UpdateMPUConfig(ocm_region, addr_ocm, 0x00004001, PRIV_RW_USER_RW|NORM_SHARED_NCACHE)

and I look at the config afterwards then I can see that it has changed to my desired values, so the function worked. But the next read from the OCM I still get the old cached value and not the new value the FPGA wrote to the OCM in the meantime. So I am asking what is wrong here? Is my approch totally wrong or is it just a little mistake I do not see at this moment?

For your information:

#define addr_ocm 0xfffc0000
#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/
#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/
#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/
u32 ocm_region = 9;

0 Kudos
3 Replies
Registered: ‎04-05-2014

I meet the same problem.

Please use this method:

#include "xil_mpu.h"

/* Cortex R5 memory attributes */
#define DEVICE_SHARED 0x00000001U /* device, shareable */
#define DEVICE_NONSHARED 0x00000010U /* device, non shareable */
#define NORM_NSHARED_NCACHE 0x00000008U /* Non cacheable non shareable */
#define NORM_SHARED_NCACHE 0x0000000CU /* Non cacheable shareable */
#define PRIV_RW_USER_RW (0x00000003U<<8U) /* Full Access */

Xil_SetMPURegion(0xFFFC0000, 0x40000, 0x30C);

Registered: ‎05-31-2012

@saberiandy  Huge solution thank you!

By the way is it safe to use OCM? I know that is used from FSBL to ATF and i'm using DDR at the moment

0 Kudos
Registered: ‎03-12-2013

I have the same question as @mrbietola. Is it safe to use OCM for communication between the A53 and R5 cores if they're both running baremetal apps?

0 Kudos