MUX EMIO driven

[aster_gio]

Hello people,
My system is composed of 4 IP blocks, eachone has a 32 bit output port. These are multiplexed and the output of multiplexer is connected to the EMIO of the zynq7000. I connected the driving signal of the Multiplexer at EMIO (output) port ( as In figure).
Based on what I read this doesn't work, it creates conflict because the 2 bit assigned for S(mux's driving signal) are also part of 32 bit in input. Is there anyway to assign the pins to use or to avoid the conflict?

P.S I can't  use AXI, I must use GPIO(EMIO) or others connection

[hbucher]

Why exactly can't you put your MUX input on GPIO2 (instead of led_4_bits) and your input at GPIO1 (instead of dip_switches_4bits)?

[aster_gio]

Thank you for the answer. Can I do that directly?
As I said I must not use the AXI port for this MUX.

[aster_gio · Accepted solution]

I solved my problem. I made a customizable block that simply take n+j bit in input (n=number of bit to read ; j= number of bit of the mux selector) and in output has j bit to drive the mux, these bit are last  j bit of the word n+j . In this way, I drive only the two last bit (as output pin) of the EMIO and I don't create conflict between Input and output. See the figure for an example.

[hbucher]

@aster_gio

You can use the standard "Slice" for bit ripping

https://www.xilinx.com/products/intellectual-property/xlslice.html

[aster_gio]

Thank you @hbucher, I don't why I didn't find that IP before, however it has the same function of my block, so I will use also  it.
Thank you for the tip!