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davewarren
Explorer
Explorer
7,167 Views
Registered: ‎03-13-2014

Making a AXI to native Fifo

Hi,

 

Can anyone give me some hints on making a AXI (stream or memory mapped) to native FIFO. The IP catalogue has options for native and AXI ports but not a way to mix them. I would like to move data from the PS to PL through a FIFO.

 

I am guessing that I should use the stream type because it would have flow control (full, empty ect)

 

I am using Vivado 2014.1 web edition

 

Thanks

 

Dave Warren

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8 Replies
yenigal
Xilinx Employee
Xilinx Employee
7,161 Views
Registered: ‎02-06-2013

Hi

 

You can use the AXI Memory mapped or AXI stream options present in the FIFO generator core directly or the AXI steam fifo.

 

Check PG057 and PG080 for more details.

 

 

Regards,

Satish

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siktap
Scholar
Scholar
7,134 Views
Registered: ‎06-14-2012

If you are looking from PS to PL through FIFO, the best option will be AXI stream FIFO.We already have had users use this.

 

http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/PS-to-PL-stream-interface/td-p/422595

 

Hope this helps . You can also also think of DMA solutions.

 

Regards

Sikta

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5,389 Views
Registered: ‎09-16-2015

Hi ,
Even I have the same requirement
@ Satish,
i went through the documents you mentioned but Im not getting how to design
@davewarren
did you find the solution for the requirement,if so please share the details

 

Regard's

Vinay

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u24c02
Adventurer
Adventurer
3,923 Views
Registered: ‎04-22-2016

Hi ,


I have the same requirement, did you find the solution for the requirement? if so please share the details

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helmutforren
Scholar
Scholar
3,341 Views
Registered: ‎06-23-2014

As I read it, the original poster wants a module with AXI on one side and native FIFO on the other side.  The FIFO Generator can do either native or AXI, but can't mix them.  Is there an easy solution to mixing them?  Without it, I would need to maybe write an in-between-module that could convert between AXI-Stream and native FIFO signals, which are indeed very similar.  I'd rather not have to write this, however.  Any suggestions?

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johnmcd
Xilinx Employee
Xilinx Employee
3,336 Views
Registered: ‎02-01-2008

Have you looked at the axi4-stream fifo PG080?

 

It is axiLite or Axi4 to Axi stream. Axi stream interface is basically a fifo interface. For example, on axi4 to stream, VALID is basically fifo not empty, and READY represents fifo read.

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helmutforren
Scholar
Scholar
3,336 Views
Registered: ‎06-23-2014

Yes, I've looked at that.  What you describe is exactly what I've already envisioned but would like to avoid doing -- building a middle module to convert AXI-Stream handshake to native FIFO handshake.

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johnmcd
Xilinx Employee
Xilinx Employee
3,322 Views
Registered: ‎02-01-2008

A simple method would be to use IPI HDL Modules. You would add an hdl file to your project that converts the signals, and then add it as a module to IPI. No need to repackage and create a new IP.

 

And if you don't want to use module flow, then I suggest to use IP packager to create a new IP and enable an AXI4 slave interface. I believe the example hdl generated for the core will infer a bram that you can read/write via AXI4. Then just modify that source to remove the bram inference and add your fifo interface.