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Registered: ‎10-29-2018

Marvell 88EA6321 connected to GEM0 in ZqnqMP

I am working on a board with Marvell 88EA6321 chip connected to GEM0 via RGMII and MDIO to GEM0.

It is a 7 port switch with Port 0, 1, 2 and 5 connected to FPGA and not much of a concern at the moment since we are only at the initial bring up stage. Port 6 connects to the CPU and Port 3 and 4 connect to the external connectors. The switch itself has only one MDIO interface with an address of 0x1. I want to bring up the Ethernet connection between the CPU and external connectors.

Currently, using the Xilinx SDK 2018.2 and the corresponding image is build with Xilinx's Yocto v2018.2 release.

I have been unable to bring this interface up. Trying to ping or receive anything does not work with the interrupt count not increasing while checking in "/proc/interrupts". In going through the forum posts, I came across the below link

https://forums.xilinx.com/t5/Embedded-Linux/Problem-with-Marvell-88E6320-connected-to-GEM3-in-ZynqMP/m-p/902612

I have a device tree entry similar to that, though I am using GEM0 and this Marvell chip does not seem to have a separate driver, so for compatible I have specified "ethernet-phy-ieee802.3-c22" and the PHY mode as RGMII instead of SGMII.

In the replies, it is mentioned to use the patch, adding the MDIO driver for accessing multiple PHY's. Also, the MACB Xilinx wiki page below mentions "Support for single MAC managing multiple PHYs is not yet merged".

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841740/Macb+Driver#MacbDriver-MissingFeatures,KnownIssuesandLimitations

The patch referenced does not apply to the kernel version currently used with 2018.2 release. I can do the changes manually and include the referenced driver, but, before embarking on that journey, I had the questions.

1. Considering our use case, I wanted to confirm if the information on that forum post and specifically the driver, is it applicable to us? Do we need to include that MDIO driver to make our use case work? Does Xilinx have an ETA on merging this work downstream or upstream?

2. Does anybody have experience in using the mentioned Marvell switch before? I see no driver for it in the downstream Xilinx tree or in the mainline. My FPGA engineer colleague who works on the FPGA side of things, says no driver should be required, however, I am not sure if that is the case.

 

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Registered: ‎02-01-2013

 

I can't say how many times I've encountered a manager, grinning and wringing his hands, dreaming of the nickels he plans to save by not putting a PHY between a Zynq and an Ethernet switch. Then I tell him of all the grief and anguish the SW team will encounter, as they try to get the latest release of Megalinux running with a phy-less Ethernet connection.

Things might be better these days, but I haven't had to deal with this problem in a while. If there isn't an explicit mode to support the phy-less connection, the SW needs to be modified (aka hacked) to bypass all of the 'normal' PHY communications--since there's no normal PHY to communicate with--and just assume a connection is present.

-Joe G.