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Observer
Observer
2,778 Views
Registered: ‎11-26-2018

Maximum output clock frequency of Zynq-7000 AP SoC?

I'm developing an oscilloscope daughterboard for the Zedboard (connected via FMC) which has a Zynq-7000 SoC. I need to clock the ADC on the daughterboard at 1 GHz. From the Zynq - 7000 documentation it says it's processing system's PLLs can generate frequencies up to 1.6 GHz. So my question is, would it be possible to route this fast clock through the programmable logic fabric and out to an FMC pin to clock my ADC at 1 GHz? 

This is the chip on the Zeboard:  Zynq-7000 AP SoC XC7Z020

This is the documentation I've been reading through:

https://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf

https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

http://www.ioe.nchu.edu.tw/Pic/CourseItem/4468_20_Zynq_Architecture.pdf

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Contributor
Contributor
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Registered: ‎04-19-2016

The PLL cannot generate 1GHz, you're looking at the maximum VCO frequency. The maximum output frequency from the PLL (PLL_FOUTMAX, table 73) is 800MHz, and the maximum IO frequency for the FPGA (table 68) is 680MHz. In any case, even if they were fast enough the FPGA clocks will severely degrade the performance of an ADC running at those kinds of speeds because they're too jittery. Very roughly, it has ~10ps rms jitter, which will give you an ENOB of 4 bits. You'd usually want some kind of clean, low jitter clock generation solution, though it depends on what level of performance you need for your application.

Observer
Observer
2,743 Views
Registered: ‎11-26-2018

Okay thank you, that makes sense. I suspected this might be the case. 

Do you think feeding an a slower FPGA clock through a pll/jitter cleaning device such as this ( http://www.ti.com/lit/ds/symlink/cdce62002.pdf ) to generate a 1 GHz for the ADC is a viable solution?

Or would it make more sense to just have a VCO and PLL on my daughterboard for a dedicated ADC clock?

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Contributor
Contributor
2,738 Views
Registered: ‎04-19-2016

Yeah you can do that, you just need to check the jitter cleaner performance is good enough. The jitter cleaners are a VCO/PLL, so it's the same thing in the end. Most ADCs have a clock output associated with the data interface which you'll need to feed back into the FPGA to capture the data anyway, so you might find it easier to generate the clock on the daughterboard and clock all the FPGA logic from the data clock instead.