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Explorer
Explorer
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Registered: ‎05-11-2012

MicroBlaze Local Memory Configuration (14.5)

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I am using EDK 14.5.  I have noticed that in the Base System Builder, that the maximum local memory can be set to 128 KB with an even distribution of 64 KB for the ICache and DCache portions of MicroBlaze.

 

Once the MicroBlaze has been configured, it appears that I can increase the size of the microblaze_0_d_bram_ctl and microblaze_0_i_bram_ctl to a total of 1 MB, but the max cache size that can be set for the ICache and DCache in the MicroBlaze still remains 64 KB.  

 

What are the implications that could arise if I increase the size of the bram controllers mentioned above to 512 KB and leave the ICache and DCache set to 64 KB within the MicroBlaze?

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Scholar
Scholar
10,704 Views
Registered: ‎02-27-2008

g,

 

If it will not fit entirely into BRAM, then you should have cache.  If it fits in BRAM, then the smallest cache, or no cache at all is required.

 

If it will not fit, then use the largest cache (if you don't know how big it should be), and use of internal BRAM is not even needed.  One can experiment with adding internal BRAM to see if it will improve performance in the DDR memory case, but as long as you have enough cache, it is unlikely to add much in the way of performance.

 

Use of internal BRAM really becomes the ROM part, or the startup code which needs to start things going (go get the program from flash, put it in DDR, etc.) when the entire application is too big to fit in BRAM.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
7,473 Views
Registered: ‎02-27-2008

g,

 

Cache is meant to optimize performance when accessing memory that is not on chip, DDR, for example.


Using BRAM on chip means that the memory is as fast as it can be, and cache is no faster, so inproving performance by using cache will be minor (if any, at all).

 

The size of the cache is usually chosen basaed on the program running:  best size means that the data and the inner program loop will completely fit in cache.  Thus size, is something only you know best.  And, if it is all BRAM, all on the device, then cache is of less value (as all BRAM is equal in speed).

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
7,467 Views
Registered: ‎05-11-2012

Hi Austin,

 

Thanks for your reply!  To make sure that I understand what you are saying, the optimal size for performance would be to set the local memory of the MicroBlaze to the max of 128 KB in the BSB and have the I & D Cache set to 64 KB so that the entire memory space is able to be cached?  If my application file needs to exceed this 128 KB limit, then I can do so as I previously mentioned but now the entire memroy space will not be cached and I could see performance degredation?  

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Scholar
Scholar
10,705 Views
Registered: ‎02-27-2008

g,

 

If it will not fit entirely into BRAM, then you should have cache.  If it fits in BRAM, then the smallest cache, or no cache at all is required.

 

If it will not fit, then use the largest cache (if you don't know how big it should be), and use of internal BRAM is not even needed.  One can experiment with adding internal BRAM to see if it will improve performance in the DDR memory case, but as long as you have enough cache, it is unlikely to add much in the way of performance.

 

Use of internal BRAM really becomes the ROM part, or the startup code which needs to start things going (go get the program from flash, put it in DDR, etc.) when the entire application is too big to fit in BRAM.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Xilinx Employee
Xilinx Employee
7,434 Views
Registered: ‎08-06-2007

Hi,

 

The local memory (LMB) is not cached and has 1 clock cycle access time.

Cache are useful when you have external memory where access time can be many clock cycles.

 

Göran