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Registered: ‎04-03-2008

MicroBlaze Maximum frequency in XPS targeting Virtex5



 While Making an EDK project with Microblaze and its peripherals, targeting the Virtex5-SX95 (xc5vsx95t ff1136 -1), the GUI shows In the System Clock frequency drop-down list that the maximum frequency is 125MHz corresponding this FPGA, can we adjust it to 235 MHz frequency to get the max 280 DMIPS ? (regarding the MicroBlaze Soft Core Processor element performance table on Xilinx website which supports Maximum Performance 280 DMIPS at 235 MHz frequency)

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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2007

It depends on the overhead of your system. MB runs at the same clock freq as PLB Bus,

If there is many perioheral on PLB Bus, MB can't reach the max freq.


Meanwhile, BSB use the restricted max freq to insure all the design generated from BSB meet the timing. As you can see the BSB design can include Memory, Ethernet, etc, this will lower the overall  freq.


So, if you are running a small system, you can change the freq in clockgenerator of  XPS/MHS directly make sure the timing meets.

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