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Observer
Observer
14,694 Views
Registered: ‎07-11-2008

Microblaze @ 200 MHz

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Dear all,

 

I've a microblaze design (mb v7.10.c, EDK 10.1 sp2) with microblaze running at 100 MHz. The whole system runs at 100 MHz. My question is, how to increase the microblaze clk to 200 MHz. I've tried to change only the CLK (of the microblaze) from "Default Connection" to a 200 MHz clock generated by 2x sys_clk_s (DCM).

But this failed. Is there any reference design to look?

 

Thanks a lot.

 

Best regards, Nico

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Observer
Observer
16,383 Views
Registered: ‎07-11-2008
My failure was, that it is not possible to run microblaze and buses with different clocks. All clocks must have same frequencies. And yes, the 235MHz are only for the fastest speed grade.

View solution in original post

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Explorer
Explorer
14,679 Views
Registered: ‎08-14-2007
It's possible that you might be more likely to get help if you could explain the problem in more detail than "this failed".  Failed how?  What happened?  Did you get synthesis errors?  Constraint violations?  Did you get a bitstream without reported errors, but it didn't execute code correctly on your target hardware?  Or did it still run at 100 MHz? It's rather hard to tell what the problem might be when the extend of the problem description is simply "this failed".
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Observer
Observer
14,659 Views
Registered: ‎07-11-2008

Hi,

 

thanks for your reply. Yes, my description is really short. I hoped, there is any example to compare.

Here is description what I've done:

 

I've generated a new project with the base system builder. I selected v5 with microblaze.

- Reference clock frequency : 100 MHz

- Processor Bus clock frequency: 100 MHz

- uartlite for IO

- no additional IPs

 

After that, it was possible to generate bitfile with bram_init (I used the generated test application).

 

My next step was, to change the microblaze clock to 200 MHz. Therefore, I created a new port at "clock generator" with 200 MHz and group PLL0 (same group as sys_clk_s, which is the 100 MHz clk). Trying to generate a bitfile failed with timing errors. So, I changed the label of the group in "clock generator" of both clks (sys_clk_s and clk200) to dcm0.

 

 BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.10.c
 PARAMETER C_DEBUG_ENABLED = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
 PORT CLK = clk200
END
 

 BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = DCM0
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PORT CLKOUT0 = sys_clk_s
 PORT CLKOUT1 = clk200
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

 

Now, bitfile generation (without program, bram init ) was succesfully. But while "init_bram", I get the following error message:

 

 ERROR:MDT - Data2Mem invocation failed.

 

When I set the CLK of the microblaze back to "default connection" (-> 100 MHz, sys_clk_s), no erros occur!

I've nothing changed in the test applicaions!

 

Please let me know, if you need more details. Thanks a lot.

 

Best regards, Nico

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Observer
Observer
14,658 Views
Registered: ‎07-11-2008

Hi,

 

I've compared the mapping report file of the version with 100 MHz microblaze clk (working) and the one with 200 MHz (data2mem invocation failed).

 

used area @ 100 MHz:

- 3x DSP48

- 2x Ramb36

- 1484 Slice Registers

- 1432 Slice LUTs

 

used area @ 200 MHz:

- 0x DSP48

- 0x Ramb36

- 80 Slice Registers

- 104 Slice LUTs

 

It seems, that the whole design is "optimized" away?!

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Explorer
Explorer
14,624 Views
Registered: ‎08-12-2007

Yes. Seems they are optimized away.

 

Since the default system clock name is "sys_clk_s", you can try to lable the 200MHz clock as the "sys_clk_s".

The bus clocks are connected to this net by default. 

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Observer
Observer
14,557 Views
Registered: ‎07-11-2008

I've tried to lable the 200MHz clock as "sys_clk_s. And added a clk100 (100 MHz) labled ckl for lmp and plb. But I got the same errors! After that, I removed the clock generator IP and added a DCM IP. But now, I get a lot of timing errors and no bitfile is generated.

 

According to the microblaze performance (Xilinx Homepage) it should be possible to get the microblaze working with 235MHz. So, 200 MHz shouldn't be too much?!

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Xilinx Employee
Xilinx Employee
14,530 Views
Registered: ‎08-06-2007

Hi,

 

235 MHz is with the fastest speed grade, is that what you have?

MicroBlaze is very configurable and enabling features on the core will slow it down.

 

Göran

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Observer
Observer
16,384 Views
Registered: ‎07-11-2008
My failure was, that it is not possible to run microblaze and buses with different clocks. All clocks must have same frequencies. And yes, the 235MHz are only for the fastest speed grade.

View solution in original post

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