cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Anonymous
Not applicable
414 Views

Microblaze Cacheable Memory External to Block Design

I have an existing block design that connects a Microblaze instance to a MIG. The I-cache and the D-cache are enabled. I want to move the MIG outside of the Block Diagram. So from the perspective of the BD, the MIG is replaced with an external axif master. And then connections to the MIG are made in the top level module the instance the BD. Once the MIG is moved outside of the BD, and replaced with the external AXI master, IP Integrator complains the interface is not cacheable. Is there a way to tell the tool that an external interface is cacheable?

 

Thanks !

 

Josh

0 Kudos
1 Reply
Highlighted
Moderator
Moderator
360 Views
Registered: ‎07-31-2012

Re: Microblaze Cacheable Memory External to Block Design

Hi @Anonymous,

 

I doubt that this approach is possible.

Could you share the screenshot of your IPI design to understand better?

 

Regards

Praveen


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos