Microblaze Cacheable Memory External to Block Design
I have an existing block design that connects a Microblaze instance to a MIG. The I-cache and the D-cache are enabled. I want to move the MIG outside of the Block Diagram. So from the perspective of the BD, the MIG is replaced with an external axif master. And then connections to the MIG are made in the top level module the instance the BD. Once the MIG is moved outside of the BD, and replaced with the external AXI master, IP Integrator complains the interface is not cacheable. Is there a way to tell the tool that an external interface is cacheable?