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Visitor
Visitor
7,263 Views
Registered: ‎06-14-2012

Microblaze Data Cache: Can't use memory below C_DCACHE_BASEADDR

I've got a custom Spartan 6 board with some custom logic and a Microblaze processor.

 

There's a DRAM connected with address range: 0xA8000000 - 0xAFFFFFFF.

 

The default configuration sets:

  • C_DCACHE_BASEADDR = 0xA8000000
  • C_DCACHE_HIGHADDR = 0xAFFFFFFF

However I need to use some of the DRAM to share data between the MicroBlaze firmware and the custom logic, so the data cache is not currently enabled (I removed the call to microblaze_enable_dcache()).

 

I'd like to use the data cache for a specific range of memory so I changed the configuration so that only the upper half of memory is cached:

  • C_DCACHE_BASEADDR = 0xAC000000
  • C_DCACHE_HIGHADDR = 0xAFFFFFFF

With this configuration and the data cache disabled, now I can't read and/or write to addresses below 0xAC000000 (i.e in the range (0xA8000000).

 

I'm not sure how adjusting the cachable region would have an effect without enabling the cache. I'm I configuring the cachable region incorrectly?

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7 Replies
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Xilinx Employee
Xilinx Employee
7,243 Views
Registered: ‎07-30-2007

In general, addresses must be 2^n. I'm not sure if that limitation applies to the microblaze cache regions, however.

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Xilinx Employee
Xilinx Employee
7,225 Views
Registered: ‎08-06-2007

Hi,

 

The address range setup with C_DCACHE_BASEADDR and C_DCACHE_HIGHADDR defines the memory range that will use the AXI_DC port. No addresses outside that address range will use that port.

 

This is how data addresses decoding is done in MicroBlaze (for data accesses, instructions are similar).

1. Check if the address is within the address range for DLMB

2. At the same time check if the address is within the range for the DCACHE and dcache is enabled

3. If neither DLMB or DCACHE, use the AXI_DP port for the access.

 

The 2) above has a twist when data cache is disabled.

If the data address is within the DCACHE address range but dcache is disabled so will normally AXI_DP be used.

But when the parameter C_DCACHE_ALWAYS_USED is set will the AXI_DC be used even if the dcache is disabled for all addresses within the DCACHE address range.

 

For your issue:

- Is C_DCACHE_ALWAYS_USED set?

- Is AXI_DP connected to your DRAM memory controller?

 

Göran

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Scholar
Scholar
7,222 Views
Registered: ‎05-31-2012

I had a similar problem, i added a second Microblaze to a design and tried to read /write to memory always failed..

I had the option "Use cache links for all memory access" disabled, so if understand Goran explanation correctly,

my program started with cache disabled (by default) and tried to access memory with AXI_DP (but that port is connected to axilite bus and cannot access external memory) and this fails..

 

is it right?

 

in the above situation (without "Use cache links.." enabled), if i had enabled the cache after  the program was loaded (writing to the MSR register), it would have worked? 

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Xilinx Employee
Xilinx Employee
7,218 Views
Registered: ‎08-06-2007

Hi,

 

Yes, if you haven't connected AXI_DP to the external memory and also not enable C_DCACHE_ALWAYS_USED, any access when dcache is disabled will fail to access external memory.

 

Yes, if you enable dcache, all accesses to external memory within the dcache address range will be able to access external memory.

But at any time,disabling cache will make accesses to external memory to fail again.

 

 

Göran

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Visitor
Visitor
7,186 Views
Registered: ‎06-14-2012

Hi Göran,

 

Thanks for your help.

 

- C_DCACHE_ALWAYS_USED is set to 1.

- I'm not quite sure how the DRAM is wired up (I'm just the firmware guy, I'm working on finding this out). What is your suggestion for how it should be connected? The case with the data cache disabled is just a test case that I've been using temporarily. The intention is to always have the cache enabled, although I don't want it used for certain addresses (as described in my original post).

 

Matt

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Visitor
Visitor
7,185 Views
Registered: ‎06-14-2012

Oh, I think I unerstand now:

 

Previously, I've was able to access all of DRAM through the AXI_DC port -- even with the cache disabled -- because C_DCACHE_ALWAYS_USED. The addresses used for the AXI_DC port spanned all of my DRAM. 

 

Now, since I've changed the address range used for the AXI_DC port (to only half of my DRAM), I can't access DRAM outside of this range because the MicroBlaze is trying to use the AXI_DP port. I probably don't have this port connected to the DRAM.

 

Does that sound correct?

 

Matt

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Xilinx Employee
Xilinx Employee
7,180 Views
Registered: ‎08-06-2007

Yes,

 

That sounds correct.

 

Göran

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