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Visitor
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Registered: ‎11-04-2010

Microblaze ISE Flow

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I don't see how to integrate EDK and ISE when generating a microblaze embedded processor. I expected to complete the Microblaze configuration wizard and instantiate the processor in my top level module back in ISE. When I select 'Generate Netlist' back in EDK it says "The RESET or MB_RESET signal is not connected". I was going to connect it to system reset back in ISE after I instantiated it, but I can't instantiate it because it won't generate a netlist.

 

I must be misunderstanding the design flow. I already have a top module, peripheral interface, local bus, etc. in verilog. How can I integrate all of this code with a microblaze soft core? I just want the processor to be a black box with instruction bus, data bus, interrupt, clock, reset inputs, etc. Something like this in my top design:

 

aemb processor (

  .clk(wb_clk),

  .rst(system_rst),

 

etc.

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Professor
Professor
9,815 Views
Registered: ‎08-14-2007

I have ISE projects with embedded MicroBlaze in them.  I think the point you missed

is that the connections to MicroBlaze look the same within the EDK whether they

go to pins of the FPGA or to the rest of the design internal to the FPGA.  So when

instantiated fom your top level HDL code you will have all of the ports and need to

connect many of them to the chip pins.  You can add the MB to the ISE project by

adding its .xmp file.  Then you can do the normal things you do with sources in

the hierarchy like "view instantiation template", or double-click o open it in XPS.

If you have already built the hardware netlist in EDK you may need to clear those

files so it can be properly re-built from within ISE.  This is necessary to deal

with I/O port buffering.  Also note that your internal ports still need to have port

names and attributes just like the external ports in your EDK design.

 

HTH,

Gabor

-- Gabor

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Scholar
Scholar
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Registered: ‎02-27-2008

b,

 

The flow I chose to use is to import my HDL (VHDL) into the EDK, leaving EDK to handle the top level, with Microblaze and all its peripherals.


My VHDL did not connect to, nor even used the MicroBlaze (it was unrelated but performed something else very useful to be done on the design).  So, I imported it as a peripheral, with no bus, no interrupts, etc.  EDK handle that just fine, and comiles everything, and then connects it together (where appropriate).  I think the only connection from the EDK to my VHDL was the system reset.  It had its own clock, but I could have used the clock in the MicroBlaze EDK project if I wanted to (I used a separate clock becaue I had to vary that clock to find the best frequency to run my design at to meet my needs).

 

To try to use the tools in the opposite direction is not something I even thought about doing ... perhaps someone else can comment.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
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Registered: ‎11-04-2010

> To try to use the tools in the opposite direction is not something I even thought about doing

 

I guess I thought it would be like other IP core generation. When you generate a block RAM from within ISE, for example, you can instantiate the block RAM in your design after the wizard completes. It even generates a verilog (and VHDL) file to use as the module definition. I was expecting something like that and, when it didn't work that way, I really got tripped up. I've read through many tutorials and docs, but all of them seem to be in the wrong direction. I don't need a BSP, and I don't want EDK to handle all of my peripherals and busses, if I can avoid it. I just want a processor that I'll hook up in a Verilog file.

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Scholar
Scholar
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Registered: ‎02-27-2008

b,


I am sure you can do it that way.  I did not.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Professor
Professor
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Registered: ‎08-14-2007

I have ISE projects with embedded MicroBlaze in them.  I think the point you missed

is that the connections to MicroBlaze look the same within the EDK whether they

go to pins of the FPGA or to the rest of the design internal to the FPGA.  So when

instantiated fom your top level HDL code you will have all of the ports and need to

connect many of them to the chip pins.  You can add the MB to the ISE project by

adding its .xmp file.  Then you can do the normal things you do with sources in

the hierarchy like "view instantiation template", or double-click o open it in XPS.

If you have already built the hardware netlist in EDK you may need to clear those

files so it can be properly re-built from within ISE.  This is necessary to deal

with I/O port buffering.  Also note that your internal ports still need to have port

names and attributes just like the external ports in your EDK design.

 

HTH,

Gabor

-- Gabor

View solution in original post

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Visitor
Visitor
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Registered: ‎11-04-2010

Okay, I see that and that helps. Now I am having a difficult time getting access to the ports. In XPS I have made the MB_RESET and INTERRUPT ports external. There is an on-chip dual-port BRAM in my design. I want Port A of the BRAM to go directly to the instruction interface of the MB. Port B will go to the wishbone interface which also connects other peripherals. The data bus of the MB will be the bus master on the wishbone interface.

 

I added an XPS External Peripheral Interface and connected the Data Processor Local Bus (DPLB) to it. Then I made the necessary signals of the EPI external. I'll provide a bridge between the PLB and the wishbone within ISE. I think that's right so far.

 

Now for connecting the instruction bus. I thought I should be able to make the instruction local memory bus (ILMB) external as well, but I can't figure that out. The LMB datasheet says, "The LMB_V10 module is used as the LMB interconnect for Xilinx FPGA based embedded processor systems. The LMB is a fast, local bus for connecting MicroBlazeTM instruc-tion and data ports to high-speed peripherals, primarily on-chip block RAM (BRAM)." That is exactly what I want, so why can't I give the bus any external ports? Do I need to use another EPI?

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Visitor
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Registered: ‎11-04-2010

I just realized I don't even have a system clock port for the MicroBlaze, only bus clocks, and I can't figure out how to export that either. I did have the DCM and BRAM instantiated in my top file. I give up. I think I'm just going to use Base System Builder and move those elements into XPS, like all of the docs want me to. But for the record I don't think that should be necessary. I don't know why I can't just say, "Give me a processor with these parameters".

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Professor
Professor
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Registered: ‎08-14-2007

I don't know why I can't just say, "Give me a processor with these parameters"

 

I thought that is exactly what BSB is for...

-- Gabor
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Visitor
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Registered: ‎11-04-2010

"I thought that is exactly what BSB is for..."

 

You are correct. I guess I'm just having a really hard time connecting it to the rest of the system.

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Visitor
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Registered: ‎11-04-2010

In 'Port Filters' the 'Defaults' check box was not checked. Now that I checked it all of the ports are there and I can make them external. Just wow.

 

Thanks!

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