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Registered: ‎12-19-2018

Microblaze MCS load program memory

Hi Forum,


I'm currenty working on a Microblaze implementation using Vivado 2020.2 in combination with Vitis 2020.2.

I have a complete solution for a product working on an Artix 7 without processors involved.

For increased flexibility, I've added a Microblaze MCS on the block design including memory etc - see attached screenshot.


I was able to export hardware, create and compile the first hello world application in Vitis without issues.


My question is, how can I run / load the generated program code in the dedicated BRAM cell if I'm not using a debug interface?

Typically I can set a default file for a BRAM IP, but on the MB block diagram, almost all options for the BRAM are locked, including the default file.


This is the example I did follow - unfortunately it is using JTAG at the end to load the program.


In addition, I'd like to know what is the best approach to load the program memory before starting Microblaze in the final application.


Any comments or hints are very much appreciated.


THanks, all the best


Tags (2)
A walkthrough of creating a MicroBlaze soft microcontroller on a Spartan-7 FPGA. This demo uses Vivado / Vitis 2020.1 and a Digilent Cmod-S7 board.
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Xilinx Employee
Xilinx Employee
Registered: ‎11-05-2019

Hi @squaringcircle 

How about the following blog etc.?

MicroZed Chronicles: MicroBlaze and Vitis

Microzed Chronicles

Thank you

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