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Visitor
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Registered: ‎09-03-2015

Microblaze + bridge DRP + MMCM_DRP + MMCM_ADV

Hi,

 

I have a Virtex-6 and I'm working in XPS (Xilinx Platform Studio).

I have already implemented a MMCM_ADV module (with DRP) with Clock Wizard (COREgen) and I would like to reconfigure DRP port, by using C code running on Microblaze. There is XAPP878 which describes the MMCM_DRP access procedure and has a reference design which is based on state machine, and which contains a verilog header file with all the calculation/lookup functions, of course written in verilog.

 

My first question is:

How can I connected the Microblaze in my design to the MMCM_DRP? I read that there is an AXI4-to-DRP bridge in XAPP1214, but when I try to import this IP into my design, an error is generated:

 

[quote]HDL language for the peripheral (top level) design unit drp_bridge is verilog

...

INFO:EDK:3391 - Create temporary xst project file:

C:\Users\utente2\Desktop\w3_802.11_EDK_v0.71_beta\pcores/drp_bridge.prj

Compiling verilog file "C:/Xilinx/14.4/ISE_DS/ISE/verilog/src/iSE/unisim_comp.v"

Compiling verilog file

"C:\Users\utente2\Desktop\w3_802.11_EDK_v0.71_beta\pcores\drp_bridge.prj"

Compiling verilog include file

"C:\Users\utente2\Downloads\xapp1214-drp-bridge\source\packaged_ip\rtl\drp_bridg

e.v"

Module <drp_bridge> compiled

ERROR:HDLCompilers:26 -

"C:\Users\utente2\Downloads\xapp1214-drp-bridge\source\packaged_ip\rtl\drp_br

idge.v" line 672 expecting 'endmodule', found 'if'[/quote]

 

My second question is:

What should I connect to the SADDR and the SEN ports?

 

 

Thanks in advance.

 

Alice

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