I have a Virtex-6 and I'm working in XPS (Xilinx Platform Studio).
I have already implemented a MMCM_ADV module (with DRP) with Clock Wizard (COREgen) and I would like to reconfigure DRP port, by using C code running on Microblaze. There is XAPP878 which describes the MMCM_DRP access procedure and has a reference design which is based on state machine, and which contains a verilog header file with all the calculation/lookup functions, of course written in verilog.
My first question is:
How can I connected the Microblaze in my design to the MMCM_DRP? I read that there is an AXI4-to-DRP bridge in XAPP1214, but when I try to import this IP into my design, an error is generated:
[quote]HDL language for the peripheral (top level) design unit drp_bridge is verilog