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Registered: ‎11-29-2019


Hi, i have a QSPI RTL which i checked on KC705 for functionality.For this qspi the inputs are coming from the APB block. I had a seperate file from where the apb takes the address and data and sends it to the qspi block.

Now, i have to connect it to the microblaze and i have to check for the functionality.

So, i created an block design,

-> microblaze connected to adi interconnect connected to the axi apb bridge.

-> i created a ip of my qspi RTL with apb interface and qspi outputs like clk,cs,and 4 data lines.

-> i created the constraint file in this and created an ip and connected to the microblaze.

-> in the microblaze by using xil_out32 function i am passing the address and data to the qspi ip.

-> I connected the processor reset to the qspi block and i had a startup2  in the qspi block. And i connected this ip to the ila.

-> at the apb interface the signals are coming correctly but the qspi outputs are not comming except the cs . Cs is going high and low but the clock and data lines are always  0 .

-> how can i check the functionality of the qspi with the microblaze.

Thanks in advance,



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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: Microblaze

Hi @jahnavijanu.y ,

It's not clear to me if you have added ILAs to the QSPI RTL core to insure that your register reads/writes are propagating through the RTL correctly.

If you aren't familiar with adding ILAs, please refer to Chapter 10 of UG908.

Another option would be to try and simulate your MicroBlaze design. This might give you some ideas of where the logic is breaking down.



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