I am building a custom AXI IP using vivado 2018.3 tool and following Xilinx documentations. My IP has few write registers as well as few read registers. Everything work fine if I comment out the read registers but when I uncomment them I get a Multiple Driver Nets issue during implementation. Below is the code snippet in question. I tried set the redRegs port as "out" or "inout" and still same issue. Can you please comment on how I should make this assignment?
customIP : hecate generic map (CNTBITS=>CNTBITS) port map (
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