cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
759 Views
Registered: ‎03-31-2014

Multiple outstanding transactions in AXI interconnect

Hi,

I am trying to test Multiple Outstanding feature of AXI interconnect.

User connects to the Slave input of AXI interconnect.
AXI interconnect performs Clock crossing and Data width conversion and connects to DDR4 MIG on the Master Side.

In AXI Interconnect IP configuration, I changed the Acceptance parameter to 5 from 1(All sides : Master Read/Write, Slave Read/Write). Still, if multiple transactions are issued to Slave input of AXI interconnect, it is not accepting beyond 2nd transaction and behaves same as Acceptance = 1.

Is there any other parameter that needs to be programmed in Interconnect generation or in MIG IP generation that can make multiple outstanding transactions accepted at input of AXI interconnect.

Thanks,

Asan.

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
594 Views
Registered: ‎02-01-2008

Forced acceptance of 1 may occur if the datawidth converter is used in the interconnect due to the MIG datawidth, and if two masters are trying to access MIG at the same time. The datawidth converter will cause ID to be reduced, and the datawidth converter will complete a transfer from one master before allowing another transfer from a different master.

If you are testing this setup in sim, try getting rid of the datawidth converters by setting the masters to the same dwidth as the slave (MIG).

0 Kudos