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Explorer
Explorer
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Registered: ‎03-25-2010

NPI Core to MPMC in EDK. MHS bad updated

Hello

 

I am using the last version of the AR 24912 example. I followed the readme.

 

After connect my_npi to the MPMC using XPS, in memory I don't have what I expect, actually, NPI is not writing memory. I am verifying with the MDM. (mrd 0x90000000 4)

 

So I verified the MHS file and I can see that it is incomplete.

 

Actual MHS:-->

---------------------------------------------------------------------------

BEGIN my_npi
 PARAMETER INSTANCE = my_npi_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE XIL_NPI = my_npi_0_XIL_NPI
END

---------------------------------------------------------------------------

 

But in the port list of the XPS I can see all the NPI signals are well connected. look attached image.

 

Do I have to modify manually the MHS, I suppose it is done by the XPS

mhs.JPG
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Explorer
Explorer
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Registered: ‎07-08-2008

Hi,

 

I believe that mrd can generate the problem itself.

Try to verify the data in other way for example with chipscope, custom logic or simply with printf("%d\r\n" *XPAR_DDR3_SDRAM_MPMC_BASEADDR) function from MBlaze (in this case you have to watch out not to write into the .text segment of application - split the NPI and application address space).

 

Greetings, Mariusz.

--
Mariusz Grad.
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Explorer
Explorer
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Registered: ‎03-25-2010

Hello,

 

Ok I will verify with other tool like Chipscope.

 

But, I have a question about the MHS file.

 

For example in this post:

 

http://forums.xilinx.com/t5/Embedded-Processing/Can-t-write-to-memory-using-MPMC-NPI/m-p/77616/highlight/true

 

The MHS is like this:

BEGIN my_npi
PARAMETER INSTANCE = my_npi_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE XIL_NPI = my_npi_0_XIL_NPI
PORT Compare_Error = my_npi_0_Compare_Error
PORT XIL_NPI_Clk = clk_100_0000MHzDCM0
PORT XIL_NPI_Rst = Debug_SYS_Rst
END

 

 

And in this post :

http://forums.xilinx.com/t5/Embedded-Processing/NPI-addres/m-p/74296/highlight/true

 

The MHS is like this:

 

BEGIN my_npi
 PARAMETER INSTANCE = my_npi_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE XIL_NPI = my_npi_0_XIL_NPI
 PORT Compare_Error = my_npi_0_Compare_Error
 PORT Hodinky = my_npi_0_Hodinky
 PORT XIL_NPI_Clk = clk_200_0000MHzPLL0
 PORT XIL_NPI_Rst = mb_reset
 PORT system_Clk = clk_200_0000MHz90PLL0
 PORT NPI_Addr = my_npi_0_NPI_Addr
 PORT NPI_AddrReq = my_npi_0_NPI_AddrReq
 PORT NPI_WrFIFO_BE = my_npi_0_NPI_WrFIFO_BE
 PORT NPI_WrFIFO_Push = my_npi_0_NPI_WrFIFO_Push
 PORT NPI_RdFIFO_RdWdAddr = my_npi_0_NPI_RdFIFO_RdWdAddr
 PORT NPI_WrFIFO_Empty = my_npi_0_NPI_WrFIFO_Empty
 PORT NPI_WrFIFO_AlmostFull = my_npi_0_NPI_WrFIFO_AlmostFull
 PORT NPI_RdFIFO_Empty = my_npi_0_NPI_RdFIFO_Empty
 PORT NPI_RdModWr = my_npi_0_NPI_RdModWr
 PORT NPI_InitDone = my_npi_0_NPI_InitDone
 PORT NPI_Clk = my_npi_0_NPI_Clk
 PORT NPI_Rst = my_npi_0_NPI_Rst
 PORT NPI_AddrAck = my_npi_0_NPI_AddrAck_0
 PORT NPI_RNW = my_npi_0_NPI_RNW_0
 PORT NPI_Size = my_npi_0_NPI_Size_0
 PORT NPI_WrFIFO_Data = my_npi_0_NPI_WrFIFO_Data_0
 PORT NPI_WrFIFO_Flush = my_npi_0_NPI_WrFIFO_Flush
END

 

Question:

 

How should be the MHS file?

 

Thanks.

 

Best regards,

 

DABG

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Explorer
Explorer
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Registered: ‎07-08-2008

Hi,

 

Both of these designs are correct.

 

Have a look to this file:  pcores/my_npi*/data/my_npi*.mpd

There you can find definition of XIL_NPI bus. Here is the snippet:

 

## Bus Interfaces
BUS_INTERFACE BUS = XIL_NPI, BUS_TYPE = INITIATOR, BUS_STD = XIL_NPI

## Ports
PORT Compare_Error = "", DIR = O
PORT XIL_NPI_Addr = "Addr", DIR = O, VEC = [(C_PI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = XIL_NPI
PORT XIL_NPI_AddrReq = "AddrReq", DIR = O, BUS = XIL_NPI

 

 

Now whenever in MHS you connect pcore with a bus:

 BUS_INTERFACE XIL_NPI = my_npi_0_XIL_NPI

it will automatically (in the background) connect  the ports described in that MPD file.

Instead connecting manually all signals you can just connect component with a bus (which is described in a MPD file).

You can read about the purpose and syntax of MPD in chapter 3 of "Platform Specification Format Reference Manual"

 

It is also possible to overwrite bus ports.

You can do that in a way which you presented in your second snippet.

 

Now the most important thing.

The EDK tool and the MHS files allow to easily built larger (embedded) systems without worrying too much about the details. The EDK is just a tool where you can stack together few components in a nice GUI manner (drag and drop etc) without the need of manually connecting every signal by hand. It's just a one layer added to the ISE.

 

In the background the EDK is just a pure generator which reads the MHS file, the MPD cores files, and several other files and then finally it generates for them hdl/*vhd files. Once it's done the ISE tool comes to the action.

In order to understand what is happening you can always go one layer of abstraction deeper (from EDK (MHS) to ISE (VHDL)).

The most important file is the hdl/system.vhd which stubs/wraps  and connects all components together.

Here is a snippet of that file:

 

  my_npi_0 : my_npi_0_wrapper
    port map (
      Compare_Error => open,
      XIL_NPI_Addr => my_npi_0_XIL_NPI_Addr,
      XIL_NPI_AddrReq => my_npi_0_XIL_NPI_AddrReq,
      XIL_NPI_AddrAck => my_npi_0_XIL_NPI_AddrAck,
      XIL_NPI_RNW => my_npi_0_XIL_NPI_RNW,
      XIL_NPI_Size => my_npi_0_XIL_NPI_Size,
      XIL_NPI_WrFIFO_Data => my_npi_0_XIL_NPI_WrFIFO_Data,
      XIL_NPI_WrFIFO_BE => my_npi_0_XIL_NPI_WrFIFO_BE,
      XIL_NPI_WrFIFO_Push => my_npi_0_XIL_NPI_WrFIFO_Push,
      XIL_NPI_RdFIFO_Data => my_npi_0_XIL_NPI_RdFIFO_Data,
      XIL_NPI_RdFIFO_Pop => my_npi_0_XIL_NPI_RdFIFO_Pop,
      XIL_NPI_RdFIFO_RdWdAddr => my_npi_0_XIL_NPI_RdFIFO_RdWdAddr,
      XIL_NPI_WrFIFO_Empty => my_npi_0_XIL_NPI_WrFIFO_Empty,
      XIL_NPI_WrFIFO_AlmostFull => my_npi_0_XIL_NPI_WrFIFO_AlmostFull,
      XIL_NPI_WrFIFO_Flush => my_npi_0_XIL_NPI_WrFIFO_Flush,
      XIL_NPI_RdFIFO_Empty => my_npi_0_XIL_NPI_RdFIFO_Empty,
      XIL_NPI_RdFIFO_Flush => my_npi_0_XIL_NPI_RdFIFO_Flush,
      XIL_NPI_RdFIFO_Latency => my_npi_0_XIL_NPI_RDFIFO_Latency,
      XIL_NPI_RdModWr => my_npi_0_XIL_NPI_RdModWr,
      XIL_NPI_InitDone => my_npi_0_XIL_NPI_InitDone,
      XIL_NPI_Clk => clk_100_0000MHzPLL0,
      XIL_NPI_Rst => Debug_SYS_Rst
    );

 

You can see that all ports of instantiated my_npi component are wired (except Compare_error).

You can track the other end of the wire (signal) and check if everything fits as it should be.

You can read about the ports and the meaning of them in a datasheets of each component.

This gives you a better understanding of what's happening with your circuit.

 

If you want to learn about this things in a details  try to create your own Makefiles which will control this process.

That's how I did it few years ago: source code

 

Greetings, Mariusz


 

 

 

--
Mariusz Grad.
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