09-28-2017 01:59 PM
Im working on a new design for a Zynq-7000 device. Our design will use 10Gig 64/66B Aurora for streaming data to and from the device, and DDR3 1600MHz memory to offload memory demands for the datapath processing.
I have question about how I should arrange the clock tree.
Physically, there are 2 x differential reference clock sources connected to the device: 1 @ 200MHz which is used by the DDR3 Memory controller (MIG), and another @ 156.25Mhz for the Aurora GTX reference clock.
I require 1 or more internal clock domains (for sure one at 250Mhz and another at 100Mhz) for the application processing and register interface in the design.
Im wondering how I should best generate these clock sources, given the 2 external clock sources I have on the device. I know that I can use a PLL/MMCM to generate multiple clock sources, but Im not 100% sure where should I get the reference clock from for the MMCM if both the Aurora GTX common and the DDR3 MIG each require a direct input from the IBUFGDS ... can I use the output clock from the MMCM in the MIG for example, as the reference clock for another MMCM that generates the the other clocks I require? Will this have any impact on the performance Ill see with the DDR3 MIG or Aurora GTX?
Suggestions are much appreciated
09-28-2017 02:21 PM
The MGTs provide everything required to transition from one clock domain to another, so having separate clocks between high speed side and logic is usually unproblematic. The fact that you use a 156.25Mhz clock also suggests that you won't have an integral relation between this clock and your 250/100MHz clock.
can I use the output clock from the MMCM in the MIG for example, as the reference clock for another MMCM?
Yes, and that is the way I would do it. First you have a proper phase relation between MIG and your logic and you also have no problem to derive the desired clocks from the base clock.
Hope this helps,