I have created a MicroBlaze custom project without Cache in Vivado 2019.2. It has only a UART and a two bits GPIO. I have compiled the project, exported the hardware and made a simple Hello World test application in Vitis. Then, I have added the ELF file to both synthesis and simulation. The problem is that after doing all these I did not see any toggling on TX pin in simulation. I decided to monitor different bus signals in the IP block and noticed that despite normal increment of iLMB Add, there is always 0 value on iLMB DBus. Besides, ce is always 0. I don't know why Xilinx make everything complicated in every changes they make into the software? Before Vitis, it was very easy creating such simple project. Now, I have spent at least 5 hours on debugging such simple project: compiling, creating again and again. Below picture illustrates mentioned problem. It seems that despite adding that ELF file to the project Vivado has not configured the instruction RAM. Or, something else is going wrong.