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Observer
Observer
8,843 Views
Registered: ‎07-09-2015

PCAP configuration for Zynq SEM IP core

Hi,

 

I am trying to get sem ip to work on zynq.
I am following the instructions : http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/SEM-IP-Zynq-Devices/td-p/590798

 

Copying it here :
1) Read carefully the SEM IP manual (page 53-55)

2) Create a block diagram in Vivado (Zynq + AXI GPIO)

3) Create a wrapper and instance the SEM IP

4) Export the design to SDK

5) Create a code for the processor that clears the PCAP_PR bit 27 and then enables the GPIO connected to the icap_grant signal

6) Program the FPGA, open Putty and run the code

 

I have a couple of questions.
1. Once I create the wrapper, I need to instantiate the sem ip in the wrapper.v? (the wrapper will be the top module?)
2. How can I clear the PCAP bit? I have found that PCAP_PR (bit 27) is in the PS device configuration control register (DEVCFG CTRL, address 0xF8007000). Do I need to write a c code to clear this pin? Also, where to connect the GPIO to the icap_grant? So that I can make it '1' when required?

 

Thanks.

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5 Replies
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Community Manager
Community Manager
8,693 Views
Registered: ‎07-23-2012

Re: PCAP configuration for Zynq SEM IP core

#1 You need to instantiate SEM IP(along with Monitor submodule) in the top level wrapper. For guidance on instantiation, you can refer to SEM IP example design.

#2 Yes you need to write a C code to to clear PCAP bit. Refer to the attached c code that clears the PCAP bit and also injects errors.

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Observer
Observer
8,663 Views
Registered: ‎07-09-2015

Re: PCAP configuration for Zynq SEM IP core

Thank you for the reply.

I instantiated the sem core correctly.

Now, when I try to run the code, I get the following output on serial (configured to 115200)

O> 02OK

I am running the following code :

 

#include <stdio.h>
#include <xil_printf.h>
#include <xil_types.h>
#include "platform.h"
#include "xil_io.h"

int main()
{
    volatile unsigned int ctrl;
    volatile unsigned int reset;

    init_platform();
    xil_printf("Hello World\n\r");

    reset = Xil_In32(0xF8000240);
    xil_printf("RESETS: %08x\n\r",reset);

    Xil_Out32(0xF8000008,0x0000DF0DU);
    Xil_Out32(0xF8000240,0x0000000EU);  // to ensure icap_grant is 0

    ctrl = Xil_In32(0xF8007000);
    xil_printf("PCAP DEVCFG CTRL: %08x\n\r",ctrl);

    Xil_Out32(0xF8007000,(ctrl&(~0x08000000)));

    ctrl = Xil_In32(0xF8007000);
    xil_printf("ICAP DEVCFG CTRL: %08x\n\r",ctrl);

    xil_printf("ICAP granted\n\r");
    Xil_Out32(0xF8000240,0x0000000CU);  // icap_grant to 1

    reset = Xil_In32(0xF8000240);
    xil_printf("RESETS: %08x\n\r",reset);

    return 0;

}

 

(My SEM IP is configured to 100Mhz. ) I believe my UART (via Pmod USB UART) is configured properly since I get

ICAP M_V4_1

when I program the FPGA and not run the sem code.

How can I solve this error?

 

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Observer
Observer
8,606 Views
Registered: ‎07-09-2015

Re: PCAP configuration for Zynq SEM IP core

Hi,

 

Can I get some assistance on this?

 

Thanks.

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Visitor
Visitor
8,242 Views
Registered: ‎11-03-2013

Re: PCAP configuration for Zynq SEM IP core

Do you slove your questions? can you help me??

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Visitor
Visitor
1,404 Views
Registered: ‎01-29-2018

Re: PCAP configuration for Zynq SEM IP core

Hi,

Can I ask you how do you manage to solve this problem? I'm having the same output O> 02OK and I can't interact with sem...

Thanks.

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