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Explorer
Explorer
5,314 Views
Registered: ‎05-15-2009

PCIe PLB Bridge on ML605: board not detected.

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Hi,

 

I have a PCIe PLB bridge XPS design on a ML605 Endpoint, i have not changed the default *.ucf. The board is connected to a X8 slot on the PC motherboard running windows XP x64. I have noticed that this design only allows x1 (1 lane) so i set J42 to x1 (default is x8 contrary to what UG534.pdf says).

 

At power on, the FPGA is configured with the design stored in the Platform FLASH, meeting the PCIe timing requirements since the S2 DIP is correctly set to load the design from this flash with the help of the 47MHz oscillator.

 

However the board is not detected by windows nor in Windriver PCI bus scan, Why?

 

 

Best,

JM

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Explorer
Explorer
6,605 Views
Registered: ‎05-15-2009

Ok the trick was to tape the unused lanes. The PCIe bridge core uses only one lane (x1), so taping the PCIe pins from B19 and A19 to B49 and A49 did the trick. Make sure J42 on ML605 is set at the default position (x1) so that windows detects the board.

 

My design is fully working on windows x64 and i can now exchange data between both the PC and the ML605 board.

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5 Replies
Explorer
Explorer
6,606 Views
Registered: ‎05-15-2009

Ok the trick was to tape the unused lanes. The PCIe bridge core uses only one lane (x1), so taping the PCIe pins from B19 and A19 to B49 and A49 did the trick. Make sure J42 on ML605 is set at the default position (x1) so that windows detects the board.

 

My design is fully working on windows x64 and i can now exchange data between both the PC and the ML605 board.

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Visitor
Visitor
5,164 Views
Registered: ‎09-16-2010

Hi Jim,

I have the same problem. Do you physically isolate the pins with a tape? Is there way to control the number of lanes from PCIe root (PC)? Mac has a nice utility that does that: http://support.apple.com/kb/HT2838.

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Explorer
Explorer
5,161 Views
Registered: ‎05-15-2009

Hi,

 

Yes, you have to phisically tape the unused lanes as i said before. I used that regular transparent tape to cover the lanes on the pci header. If you use the PCIe bridge core, although there is an option to choose between 1, 4 or 8 lanes on the core config menu, it won't let you choose a number of lanes different than 1. The actual version of the core only supports x1.

 

 

Best,

JM

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Visitor
Visitor
5,155 Views
Registered: ‎09-16-2010

I was able to generate x8 core (v1.5) and build it. It worked on the board.

 

Ahmed

 

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Explorer
Explorer
5,152 Views
Registered: ‎05-15-2009

Yes because you probably have your board installed in a x8 slot. The point is that it will not work if you use the x1 PCIe bridge core, or other that uses less lanes, on a x8 motherboard slot. In this case you have to tape the unused lanes.

 

 

Best,

JM

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