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Visitor
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Registered: ‎04-03-2019

[PG162]AXI master burst

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Hello guys, I am reading the [PG162]"LogiCORE IP AXI Master Burst v2.0 Product Guide for Vivado Design Suite". I am confused with the timing diagram of page 31 for the burst write. The m_axi_wready holds high for only 19 cycles and m_axi_wvalid holds high for 20 cycles. According to the [IHI 0022F.b]AMBA® AXI and ACE Protocol Specification in page A3-41 from ARM, the transfer can only occur when VALID and READY are both high, which means there should be 19 data can be transferred. However, pg162 shows there are 80 bytes being transferred (20 transfers). Thank you in advance if anyone can help me figure out this problem.
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Moderator
Moderator
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Registered: ‎01-09-2019

Hello @joker0208 

I believe you are correct that the amount of transfers would be 19 which would not equate to 80 bytes with a 32-bit width interface.  I have created a change request to see if we can have that updated in the product guide.

One note is that is an older IP so might not be as useful depending on what your final application is.

Thanks,
Caleb
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Moderator
Moderator
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Registered: ‎01-09-2019

Hello @joker0208 

I believe you are correct that the amount of transfers would be 19 which would not equate to 80 bytes with a 32-bit width interface.  I have created a change request to see if we can have that updated in the product guide.

One note is that is an older IP so might not be as useful depending on what your final application is.

Thanks,
Caleb
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