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sdeyerle
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Registered: ‎03-25-2013

PL Clocks on Zynq ZC706

I've been trying to build a simple setup with XPS and ISE/PlanAhead, but it seems regardless of how I change the settings in XPS, the PL Clocks are not enabled.  I have tested this using Chipscope modules, and the clocks driving the fabric directly like USR_CLK work fine, but everything coming out of the PS (at least clock-wise) seems to be not running.

 

Am I correct in assuming the bitstream generated from an XPS project should configure the PLLs and Clocks?  It seems as though these are software accessible as well, so I want to make sure that XPS will configure the clocks as it says in the clock configuration wizard and that I don't need to generate an FSBL or something to set the clock configuration.

 

I have the Xilinx Linux build running on the ARM as well, and the behavior I'm seeing is that I can read/write from memory-mapped registers within the PS, but when I try to write to anything in the PL (which I have typically programmed after Linux boots, but also sometimes before) the system hangs and stops responding to input.  This seems like it would be explained by a non-existent clock on the AXI interconnect and peripherals, which at present are all tied to FCLK_CLK0.

 

The system I'm trying to build is just the default XPS system for the ZC706, though I have added ChipScope IP into my XPS project.  I have had the same behavior building on both Linux and Windows boxes, and I am running version 14.4 of the tools.

If anyone has any idea as to why these clocks aren't running or some blatant error I am doing, I'd appreciate your feedback.  Thanks!

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ywu
Xilinx Employee
Xilinx Employee
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Registered: ‎11-28-2007

The FCLKs from PS are configured and enabled by ps7_init.tcl (for XMD) or ps_init.c (for FSBL). They need to be run before the clocks start running.

 


@sdeyerle wrote:

I've been trying to build a simple setup with XPS and ISE/PlanAhead, but it seems regardless of how I change the settings in XPS, the PL Clocks are not enabled.  I have tested this using Chipscope modules, and the clocks driving the fabric directly like USR_CLK work fine, but everything coming out of the PS (at least clock-wise) seems to be not running.

 

Am I correct in assuming the bitstream generated from an XPS project should configure the PLLs and Clocks?  It seems as though these are software accessible as well, so I want to make sure that XPS will configure the clocks as it says in the clock configuration wizard and that I don't need to generate an FSBL or something to set the clock configuration.

 

I have the Xilinx Linux build running on the ARM as well, and the behavior I'm seeing is that I can read/write from memory-mapped registers within the PS, but when I try to write to anything in the PL (which I have typically programmed after Linux boots, but also sometimes before) the system hangs and stops responding to input.  This seems like it would be explained by a non-existent clock on the AXI interconnect and peripherals, which at present are all tied to FCLK_CLK0.

 

The system I'm trying to build is just the default XPS system for the ZC706, though I have added ChipScope IP into my XPS project.  I have had the same behavior building on both Linux and Windows boxes, and I am running version 14.4 of the tools.

If anyone has any idea as to why these clocks aren't running or some blatant error I am doing, I'd appreciate your feedback.  Thanks!




Cheers,
Jim
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bmagnuson
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Registered: ‎03-06-2013

I'm having the exact same problem and I've been able to make no progress.  I'm booting over SD and I'm quite sure that the FSBL is executing*.  The only write that I see to any FCLK0 registers in ps7_init.c is to 0xF8000170 (FPGA0_CLK_CTRL) which sets up the divisors and source select (IO/DDR/CPU).

 

I can read back this register once Linux boots and everything appears to be ok except that FCLK0 is definitely not running.  I've routed it out to a SMA on the zc706 and it's a static 0.

 

Are there other registers that should be written to enable the FCLK outputs?  I've tried poking at FPGA0_THR_CTRL and FPGA0_THR_CNT to no avail.  Interestingly FPGA0_THR_STATUS always reads back 0x10000.  The set bit indicates that 'Clock is running in debug mode (Keep configuration static).'  This seems odd and raises two questions.

 

1) What is 'debug' mode?

2) How do I get out of it?

 

* This appear in my serial terminal

 

 

Xilinx First Stage Boot Loader
Release 14.5/2013.1 May 6 2013-16:07:16
Silicon Version 2.0
Boot mode is SD
SUCCESSFUL_HANDOFF
FSBL Status = 0x1

 

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sdeyerle
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Registered: ‎03-25-2013

Write 0xF to 0xF8000900 (LVL_SHIFTR_EN).  That was my problem.  The default FSBL only enables the PS<->PL Level shifters if a .bit file is included in BOOT.BIN.  You have to enable it manually otherwise (or modify the bootloader).

bmagnuson
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Registered: ‎03-06-2013

Yes!  That did the trick.  Thanks so much.  Less than 15m turn around time.  That's what I call efficient.

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sdeyerle
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Registered: ‎03-25-2013

Haha, I wish that problem only took me 15 minutes to figure out...

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bmagnuson
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Registered: ‎03-06-2013

Still no love actually.  I clearly now have a functioning clock but all attempts to access the peripheral AXI bus still hang.  This happens from within Linux (mmap) or u-boot (md.l).

 

Something strange I noticed is that all of the 'suppors read'/'supports write' boxes are unchecked in the configuration dialog for my AXI interconnect in XPS.  While that seems to be an obvious problem there are two issues:

 

!) Attempting to check those boxes causes the 'busy' cursor to pop up and never go back to idle. I can still click 'ok' or 'cancel' and the dialog will close.  However, the boxes will still be clear if I reopen the dialog.

 

2) The module parameters in the generated HDL seem to indicate that these read/write settings are in fact enabled despite what the GUI is reporting.

 

So still in the wilderness on this one.  Any other magic enables I should be hitting?

 

 

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sdeyerle
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Registered: ‎03-25-2013

I didn't have any problems like that.  Are you doing this in XPS?  The default XPS design with DIP switches and LEDs should work right out of the box.  (At least it did for me)

 

Also, try putting a Chipscope AXI monitor in your design.  That may help you figure out where your problem lies.

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sathaps2
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15,904 Views
Registered: ‎05-06-2013

Hi Sdeyerle & Bmagnuson,

    I am also into the same problem. I could see signals coming from PL to the PS. But, I cannot write signals from PS to PL.

 

    I was looking into the FSBL as suggested, for the LVL_SHFTR_EN signal. What exactly is the change I need to make?

    I could see this LVL_SHFTR_EN signal being used in two places :

    1. FabricInit(writing value 0xA to register 0XF8000900)

    2. EnablePLtoPSLevel_Shifter(writing value 0xF to register 0XF8000900)

   

I am stuck with this issue for more than a week. Which function do i need to write this 0XF, as you mentioned?

 

Best Regards,

Thanks in advance..

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swordfishman
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Registered: ‎05-29-2013

I have a similar issue.  My HW engineer has changed his PL clocks and exported the design to SDK.  I then build a new FSBL and update my BOOT.bin.  I can see that the clocks are running at the updated rates but uboot no longer executes.  Any thoughts?

 

Cheers,

Benjamin

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muzaffer
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Registered: ‎03-31-2012

There are signals coming from the PL side which cause interrupts to the PS. Make sure PL instantiation writes all inactive values to them otherwise your PS will hang.
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anfatec
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Registered: ‎08-27-2011

I had the same problem with an almost empty design (in PlanAhead 14.6), just a CLK from PS to PL.

The ps7_init.tcl  script was ok; but still no clock in the PL.

After adding a gpio_GPIO_pin  in XPS, retranslation (.. export to SDK ..).. the clock were working.

 

 

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neowt
Adventurer
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Registered: ‎08-08-2008

Hi all,

  I just solved a similar issue in SDK 2014.4.  I was running in debug mode in SDK.  The problem was ps7_post_config was not ran.  

  The clock is not enabled if I right click on application project --> Debug As --> Launch On Hardware (GDB).  However, if right click on application project --> Debug As --> Debug Configurations --> Xilinx C/C++ Configurations --> New -->Debug.

 

  Seems like the second way will run ps7_post_config.

 

  Hope it helps.

 

Neo

 

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tomasz.janicki.tj
Adventurer
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Registered: ‎01-09-2014

I am using Vivado 2015.4.2

I am using SDK 2015.4 

Xilinx SDK    1.0.0.201511181701    com.xilinx.sdk.product.plugin    null

Quest OS: Ubuntu 12.04

Host OS & Hypervisor - I do not even know... sorry

JTAG is conneted to Windows PC  running hw_server (LAB edition)

 

 

What was easier* for me:

1) Implement & Generate Bitfile of your design in Vivado

2) Export to Hardware (include bit file)

3) Launch SDK (localy in project)... HW platform with system.hdf shoukd be availble shortly after

4*) In Target Connections make sure you have your remote target selected if not create one (slelect propper freq as well)

5) New -> Application (create new BSP - do NOT first create BSP then select it, Create NEW BSP)

  -  select FSBL

6) Comile

   - compilation by default starts automatically so no need to click on anything.

7) Run or right-click your FSBL app and Run As

   - play with both if you need to and when using Run As select your desired configuration...

            ... I slelected Launch on Hardware "System Debugger"

   - It will rant about ther FPGA not configured - click OK

8) Now you can program Device even in Vivado

  - no need to export Hardware as long as you do not do anything that FSBL needs to catch up

  - you can always also program FPGA via SDK... but what for? Just compile and run FSBL once (per powr-up that is)

 

Now you know the steps :) ... anyone can help with providing bash/tcl script for all that - I hate clicking on everything

 

 

*easier - for some reason the steps provided on this thread did not work for me.

What seems to work for me was "FSBL flow". What did not work for me was "JTAG Init"

 

4*) - this step needs to be done before 7)if you also program remote target it is 4 becouse I like it to be 4 :)

 

... remote needs to run

[Vivado dir]/bin/hw_server.bat    - if WIN ... maye you can run bash script if you have cygwin?

.[Vivado dir]/bin/hw_server    - if Normal OS :)

 

 

With Regards

T

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tomasz.janicki.tj
Adventurer
Adventurer
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Registered: ‎01-09-2014

Created small XSDB TCL code

run ie:

 

xsdb jtag-fsbl.tcl x2015 images tcp:192.168.18.125:3121

script:

 

 

set expectX [lindex $argv 0]
set ChoiceElf [lindex $argv 1]
set HWS [lindex $argv 2]

set AvnetX ""
set Elf ""


if {$argc < 3} {
	puts "MISSING ARGUMENTS"
	puts "x2014/x2015 pre-built/images HW_Server_IP" 
	exit
}

if {$expectX eq "x2014"} {
	set AvnetX "PicoZed_2014.4_Avnet"
}

if {$expectX eq "x2015"} {
	set AvnetX "PicoZed_2015.4_Avnet"
}


if {$ChoiceElf eq "pre-built"} {
	set Elf "pre-built/linux/images/zynq_fsbl.elf"
}

if {$ChoiceElf eq "images"} {
	set Elf "images/linux/zynq_fsbl.elf"
}



cd ~/ZYNQ/$AvnetX/pico-hardware


connect -url $HWS
targets -set -nocase -filter {name =~ "arm*#0"}

source subsystems/linux/hw-description/ps7_init.tcl; ps7_post_config
catch {stop}
set mctrlval [string trim [lindex [split [mrd 0xF8007080] :] 1]]

puts "mctrlval=$mctrlval"
puts stderr "INFO: Downloading ELF file to the target."
dow "$Elf"

after 2000
con
after 3000
exit

 

Im using petalinux 2014/2015 and remote server (WIN7)

Script just boots fsbl (from pre-built or from images) - fsbl.elf is on Linux machine

Feel free to tweak it. 

 

Main part of this script is generated by ie:

 

petalinux-boot --jtag -v --hw_server-url tcp:192.168.18.125:3121 --prebuilt 1 --tcl jtag-fsbl.tcl

one can generate other scripts - ie also for BIT, kernel, uboot and other.

 

petalinux-boot --jtag can however boot BIT, kernel, uboot without problems - only fsbl is strange with this additional line :

 

source subsystems/linux/hw-description/ps7_init.tcl; ps7_post_config

and the line needs to be added after connect so you can not use

 

--xsdb-conn paramater to the petalinux-boot --jtag

 

 

T

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fafactx
Visitor
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Registered: ‎09-24-2018

 its easy to r/w any ps register in linux. you can enable devmem cmd in rootfs.

than, devmem addr 32 [option] 

addr maybe ps register example 0xf8000900  option may value to write or dummy date .

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