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Ankush
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Registered: ‎10-27-2020

PL to PS interrupt generation signalling

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Hi,

 

I have developed a custom RTL module in PL which generates an interrupt to the PS on an event. I would like to know the signalling format for a level triggered interrupt signal generation.

1. For how many clock cycles should it be high to get successfully detected on PS side?

2. What should the reference clock used to generate this interrupt signal?

I am using Zync Ultrascale+ MPSoC for my design.

 

Thanks and Regards 

Ankush 

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stephenm
Xilinx Employee
Xilinx Employee
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Registered: ‎09-12-2007

This is documented in the TRM for the Zynq Ultrascale (chapter 13):

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

gic.PNG

The other considerations are that the bsp used in Vitis (baremeral), or the devicetree generator used in Petalinux (linux) will only detect ports of type INTERRUPT when populating the xparameters.h and the devicetree node respectively. So, make sure that you set the port type to INTERRUPT when packaging your RTL. Otherwise you will manually need to populate the interrupt info.

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stephenm
Xilinx Employee
Xilinx Employee
296 Views
Registered: ‎09-12-2007

This is documented in the TRM for the Zynq Ultrascale (chapter 13):

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

gic.PNG

The other considerations are that the bsp used in Vitis (baremeral), or the devicetree generator used in Petalinux (linux) will only detect ports of type INTERRUPT when populating the xparameters.h and the devicetree node respectively. So, make sure that you set the port type to INTERRUPT when packaging your RTL. Otherwise you will manually need to populate the interrupt info.

View solution in original post

Ankush
Visitor
Visitor
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Registered: ‎10-27-2020

This was helpful, thank you for the super quick response:)

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stephenm
Xilinx Employee
Xilinx Employee
260 Views
Registered: ‎09-12-2007

No problem. Can you marked this as solved as this might help others

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