I’m designing a custom board and FPGA based on a Zynq UltraScale+. We have an FreeRTOS based application running on the first R5 core. The application is able to handle interrupts(e. g. our UART driver is interrupt based) and so for everything is working just fine.
Recently I tried adding a custom SPI core to the design which I’m sure is working because I used it in around 15 other (microblaze) designs without any issues. Interrupt inputs from PL are set to rising edge.
After some difficulties because I didn’t ended up in the ISR (driver is an exact copy from microblaze as well) after the transfer I digged a little deeper into the PL design using ChipScope and found that the IRQ was generated just perfectly but after reading the TRM once more I realized the IRQ need at least 4 100MHz clock cycles.
So I added a some logic to make the interrupt 128 cycles long (tried 16, 32 and 64 first) and now it is working.
My first thought was that this needs to be related to the GIC clocking but I’m not able to find out how to configure the GIC clock. The only information I was able to find is that this clock is derived from the LSBUS but I’m missing the exact relation here. Anyway, the LSBUS is set to 100MHz in my design. I think this is correct.
Does anyone know how to check if the GIC is running at the correct frequency?
Another question: In all examples I see concats placed in between the Port and the UltraScale+ interrupt input. In my design I skipped this and connected the interrupt ports of the block design directly to the CPU. Might this be an issue? I mean, I don’t know why but this is a clear difference from what I can find on the web regarding examples.
And I’m almost sure that this is based on the pulse length because I added an interrupt which either 16 (32,64) cycles or 128cyles I can trigger by a command choosing if I’d like to have the short or the long one. Long one always worked. Short one didn’t when <= 32 and did work most of the time when using 64 cycles. But it fails sometimes.
I mean I can add such logic to all interrupt but first of all it will decrease the performance and second it’s a little frustrating not to know why this happens and where to find this in the documentation. Any ideas?