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Registered: ‎03-08-2019

PLB address decoding

I've had a Spartan6 design thrown over the wall at me and my first step in understanding the operation is to review the HDL.  The design instantiates a Microblaze core with a PLBv4.6 interface.  One of the user cores includes a register interface accessable from the microblaze via PLB.  In the user core HDL the registers are selected by a value on a bus called Bus2IP_WrCE.

It looks like this Bus2IP_WrCE bus is one-hot encoded, so each register is accessed when a specific bit on Bus2IP_WrCE is active.  What I can't tell from this is how the values on Bus2IP_WrCE map to actual numerical address (what address is accessed via the microblaze to talk to a specific register?).

Bus2IP_WrCE is 32 bits wide, and Bus2IP_Data is 32 bits wide (4 bytes).

Can someone please explain how the PLB address but is encoded to create Bus2IP_WrCE?



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Xilinx Employee
Xilinx Employee
Registered: ‎02-01-2008

Normally, a register is expected to be 32bits of data. A single CE would access one 32bit register.

But, there are a bunch of arrays that are used by the IPIF address decode logic.

Checkout the docs for the PLB IPIF. I found one  here:

There will be an array for assigning address offsets for one or more chip selects, and there will be an array for assigning how many chip enables per chip select.

So if a chip select is setup to have an address range of 128, and that same chip select is configured to have 8 chip enables, then each CE within that address range will be active for 128/8 address locations.

I managed to find a very old OPB core that I had laying around and here's a quick breakdown

IPIF_ARD_ADDR_RANGE_ARRAY contains pairs of 64bit base addr and 64bit high addr. Each pair will create a CS (chip select)

IPIF_ARD_NUM_CE_ARRAY will contain a list of integer values. Each integer value represents how many CEs are within a CS addr range.

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