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lnarayanan_123
Visitor
Visitor
273 Views
Registered: ‎12-24-2020

PS AXI (S_AXI_HP1 ) Slave Port HP1 access via PL Master ( custom design) having read write mismatches

Hi All,

I have developed a Custom master to access DDR3 Connected to PS . DDR3 device is 16bits wide and i have two devices connected to it. So the AXI Bus Width is configured as 32bits.

In the Address editor of Block design assigned address is 0x0_0000_1000_0000 --> 0x0_0000_1FFFF_FFFF.

DDR is accessed by software for booting purpose only.

AxSize = 2  [ 4 Bytes = 32bits in a beat ]

AxBurst=1   [ INCR] 

AxLen = 7   [ Length = 8 ] 

Write Transaction

lnarayanan_123_0-1615212055388.png

Read Transaction

lnarayanan_123_1-1615212083824.png

If the waveform is not clear i am putting in a tabular form as below:-

WRITE

READ

0000 A5A5

0003 FFFF

0001 5A5A

0003 FFFF

0002 A5A5

0003 FFFF

0003 5A5A

0003 FFFF

0004 A5A5

0007 FFFF

0005 5A5A

0007 FFFF

0006 A5A5

0007 FFFF

0007 5A5A

0007 FFFF

 

Is there anything i am missing in the AXI protocol Master design to do any write or read transactions with respect to the DDR Interface access. 

 

 

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1 Reply
katsuki
Xilinx Employee
Xilinx Employee
170 Views
Registered: ‎11-05-2019

Hi @lnarayanan_123 

It is difficult to develop the AXI protocol from scratch.

I recommend that you use the Vivado Package IP Wizard to create a simple AXI master IP and start with this IP as a starting point.

UG1118 Vivado User Guide - Creating and Packaging Custom IP

The following Blog and Forum are also good references.

AXI Tutorials

AXI Basics Series

Thank you.


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