I have developed a Custom master to access DDR3 Connected to PS . DDR3 device is 16bits wide and i have two devices connected to it. So the AXI Bus Width is configured as 32bits.
In the Address editor of Block design assigned address is 0x0_0000_1000_0000 --> 0x0_0000_1FFFF_FFFF.
DDR is accessed by software for booting purpose only.
AxSize = 2 [ 4 Bytes = 32bits in a beat ]
AxBurst=1 [ INCR]
AxLen = 7 [ Length = 8 ]
If the waveform is not clear i am putting in a tabular form as below:-
Is there anything i am missing in the AXI protocol Master design to do any write or read transactions with respect to the DDR Interface access.
It is difficult to develop the AXI protocol from scratch.
I recommend that you use the Vivado Package IP Wizard to create a simple AXI master IP and start with this IP as a starting point.
UG1118 Vivado User Guide - Creating and Packaging Custom IP
The following Blog and Forum are also good references.
AXI Basics Series