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sjjma
Observer
Observer
8,081 Views
Registered: ‎05-16-2012

PS_MIO pins not available to PL, why ?

I'm surprised that the PS_MIO pins cannot be used by the PL. It's a fair number of pins that would come in handy.

Considering how fast the 7 series LUTs are, fairly complex filtering or checking/modifications of the PS_MIO signals

can be done by the PL before passing onto the processor.

 

What's the reasons for this decision ?

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7 Replies
achutha
Xilinx Employee
Xilinx Employee
8,078 Views
Registered: ‎07-01-2010


Hi,

The MIO is fundamental to the I/O peripheral connections due to the limited number of MIO pins. Software programs the routing of the I/O signals to the MIO pins. The I/O peripheral signals can also be routed to the PL (including PL device pins) through the EMIO interface. This is useful to gain access to more device pins (PL pins) and to allow an I/O peripheral controller to interface to user logic in the PL.

Are you aware of the PS EMIO Interface? I guess you are referring to this connection.

Refer to link for more details: details:http://www.xilinx.com/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf

Regards,
Achutha
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sjjma
Observer
Observer
8,054 Views
Registered: ‎05-16-2012

Figure 2 on page 9 of the overview pdf you pointed shows that the MIO pins associated with the Ethernet, USB, etc.

are NOT accessible by the PL.  My point is that pins are valuable & should be usable by the PL ( which is the real

attraction of Xilinx & not the arm ).

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muzaffer
Teacher
Teacher
8,030 Views
Registered: ‎03-31-2012

Yes, it would be interesting to learn if it was a conscious decision or an oversight to not allow PL access to PS MIO pins. It would have needed more IO between PS and PL and also it would have added quite a bit more bugs to the user implementation.
I suppose being able to insert PL functionality between the MIO and the PS logic was never considered at all. All the logic needed to interface with the MIO is already implemented on PS hardware and there is probably not much to be added by putting some PL block in between.
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mcgett
Xilinx Employee
Xilinx Employee
8,016 Views
Registered: ‎01-03-2008

It was a conscious decision.  The PS and PL areas are radically different and attempting to allow the PL to connect directly with the IO in the PS would have been radically different use model.  In the Zynq family the processer subsystem is the leader in the device and the design directive was to ensure that it would always be fully capable of operating without programming the PL portion.

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muzaffer
Teacher
Teacher
8,011 Views
Registered: ‎03-31-2012

>> In the Zynq family the processer subsystem is the leader in the device and the design directive was to ensure that it would always be fully capable of operating without programming the PL portion.

 

Adding a multiplexer to the PS logic to relinguish control programmatically to the PL would not break this directive. The control would always belong to PS which would let PL access the MIO or not. It is not different than using EMIO to go through PL after getting PL programmed. 

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daniel.kho
Observer
Observer
5,076 Views
Registered: ‎09-19-2012

Sorry to bring up this old thread. I just find myself so frustrated that perhaps my two cents worth of comments may prove beneficial to the folks in Xilinx when trying to cook up future device families.

I feel the fact that PS MIO pins are not available to the PL is a serious limitation in how the Zynq device can be used. There are many use cases where people would want to gain access to PS MIO pins from the PL, and not granting such access has greatly limit the power of Zynq. For my case, I would want to have dedicated PL logic to be able to gain access to the gigabit Ethernet interface on my ZC702, but the fact that this interface is routed to PS MIO pins mean that I have to use an expansion card connected to FMC (which increases my cost).

 

This forces us to use the processor to communicate through some peripherals, and could run counter to our objectives to create a high-performance system that leverages the power of custom logic within the PL fabric. Processors have the tendency to hang, and communicating with several interfaces at the same time is not what processors are typically good at doing as compared with what the PL is capable of.

 

Also, when the software hangs, from what I understand the PL could also cease to function? I think modern FPGAs should not allow dedicated hardware to fail when the processor fails. Just my two cents...

 

-dan

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hossam1984
Participant
Participant
1,123 Views
Registered: ‎02-26-2019

Hello,

even it is too late reply but it maybe useful for someone. As I was looking for a similar thing and I got the following idea. In my case I want to sniff the MIO of the ETH0.

So, I made inout port that catch the FIXED_IO MIO signals.

 

verilog code you can extend it to achieve your purpose.

module test_IO(
inout [53:0] bidir
);

 

 

Regards,

Hossam

MIO.PNG
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