05-01-2014 06:53 PM
I'm surprised that the PS_MIO pins cannot be used by the PL. It's a fair number of pins that would come in handy.
Considering how fast the 7 series LUTs are, fairly complex filtering or checking/modifications of the PS_MIO signals
can be done by the PL before passing onto the processor.
What's the reasons for this decision ?
05-01-2014 07:39 PM
05-02-2014 12:27 PM
Figure 2 on page 9 of the overview pdf you pointed shows that the MIO pins associated with the Ethernet, USB, etc.
are NOT accessible by the PL. My point is that pins are valuable & should be usable by the PL ( which is the real
attraction of Xilinx & not the arm ).
05-04-2014 08:58 AM
05-05-2014 07:58 AM
It was a conscious decision. The PS and PL areas are radically different and attempting to allow the PL to connect directly with the IO in the PS would have been radically different use model. In the Zynq family the processer subsystem is the leader in the device and the design directive was to ensure that it would always be fully capable of operating without programming the PL portion.
05-05-2014 12:35 PM
>> In the Zynq family the processer subsystem is the leader in the device and the design directive was to ensure that it would always be fully capable of operating without programming the PL portion.
Adding a multiplexer to the PS logic to relinguish control programmatically to the PL would not break this directive. The control would always belong to PS which would let PL access the MIO or not. It is not different than using EMIO to go through PL after getting PL programmed.
07-03-2016 05:33 AM
Sorry to bring up this old thread. I just find myself so frustrated that perhaps my two cents worth of comments may prove beneficial to the folks in Xilinx when trying to cook up future device families.
I feel the fact that PS MIO pins are not available to the PL is a serious limitation in how the Zynq device can be used. There are many use cases where people would want to gain access to PS MIO pins from the PL, and not granting such access has greatly limit the power of Zynq. For my case, I would want to have dedicated PL logic to be able to gain access to the gigabit Ethernet interface on my ZC702, but the fact that this interface is routed to PS MIO pins mean that I have to use an expansion card connected to FMC (which increases my cost).
This forces us to use the processor to communicate through some peripherals, and could run counter to our objectives to create a high-performance system that leverages the power of custom logic within the PL fabric. Processors have the tendency to hang, and communicating with several interfaces at the same time is not what processors are typically good at doing as compared with what the PL is capable of.
Also, when the software hangs, from what I understand the PL could also cease to function? I think modern FPGAs should not allow dedicated hardware to fail when the processor fails. Just my two cents...
07-10-2020 01:11 AM
even it is too late reply but it maybe useful for someone. As I was looking for a similar thing and I got the following idea. In my case I want to sniff the MIO of the ETH0.
So, I made inout port that catch the FIXED_IO MIO signals.
verilog code you can extend it to achieve your purpose.
inout [53:0] bidir