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Adventurer
Adventurer
1,161 Views
Registered: ‎01-28-2008

PS - PL communication

Hi,

I am trying to get a PL register access via the AXI-bus on a ZCU111 board. Unfortunately, I can't get this operation working. I thought this would be a very simple fundamental functionality and direct memory access should work without any problems. But I am struggling to get this feature working. At the most simplest level I have implemented block design (as attached). I am trying to access this via xsdb as follows:

========================================================================================================

xsdb% source ./test.tcl
100% 32MB 1.7MB/s 00:19
Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)
Downloading Program -- /work/projects/git2/Octopus/FPGA/octopus_drfm/fw/octopus_top_zcu111/vivado2018.3/octopus_top.sdk/test_a53/Debug/test_a53.elf
section, .text: 0x00000000 - 0x000015eb
section, .init: 0x00001600 - 0x00001633
section, .fini: 0x00001640 - 0x00001673
section, .note.gnu.build-id: 0x00001674 - 0x00001697
section, .rodata: 0x00001698 - 0x0000173f
section, .rodata1: 0x00001740 - 0x0000173f
section, .sdata2: 0x00001740 - 0x0000173f
section, .sbss2: 0x00001740 - 0x0000173f
section, .data: 0x00001740 - 0x0000201f
section, .data1: 0x00002020 - 0x0000203f
section, .ctors: 0x00002040 - 0x0000203f
section, .dtors: 0x00002040 - 0x0000203f
section, .eh_frame: 0x00002040 - 0x00002043
section, .mmu_tbl0: 0x00003000 - 0x0000300f
section, .mmu_tbl1: 0x00004000 - 0x00005fff
section, .mmu_tbl2: 0x00006000 - 0x00009fff
section, .preinit_array: 0x0000a000 - 0x00009fff
section, .init_array: 0x0000a000 - 0x0000a007
section, .fini_array: 0x0000a008 - 0x0000a047
section, .sdata: 0x0000a048 - 0x0000a07f
section, .sbss: 0x0000a080 - 0x0000a07f
section, .tdata: 0x0000a080 - 0x0000a07f
section, .tbss: 0x0000a080 - 0x0000a07f
section, .bss: 0x0000a080 - 0x0000a0bf
section, .heap: 0x0000a0c0 - 0x0000c0bf
section, .stack: 0x0000c0c0 - 0x0000f0bf
100% 0MB 0.2MB/s 00:00
Setting PC to Program Start Address 0x00000000
Successfully downloaded /work/projects/git2/Octopus/FPGA/octopus_drfm/fw/octopus_top_zcu111/vivado2018.3/octopus_top.sdk/test_a53/Debug/test_a53.elf
0
xsdb% Info: Breakpoint 0 status:
target 9: {Address: 0xda8 Type: Hardware}
xsdb% mrd 0x70000000 10
70000000: 00000000
70000004: 00000000
70000008: 00000000
7000000C: 00000000
70000010: 00000000
70000014: 00000000
70000018: 00000000
7000001C: 00000000
70000020: 00000000
70000024: 00000000

xsdb% mrd -force 0x80000000
Memory read error at 0x80000000. Instruction transfer timeout
xsdb% Info: Cortex-A53 #0 (target 9) Running
xsdb% Info: Cortex-A53 #0 (target 9) Stopped at 0x0 (Cannot resume. Cannot read 'pc'. Cannot read 'r0'. Instruction transfer timeout)
xsdb% mwr -force 0x80000000 0xdeadbeef
Memory write error at 0x80000000. Cannot read sctlr_el3. Cannot read r0. Instruction transfer timeout

========================================================================================================

where test.tcl contains the following:

========================================================================================================

connect
targets 4
fpga ../octopus_top.runs/impl_1/octopus_drfm_top_zcu111.bit
source octopus_drfm_top_zcu111_hw_platform_1/psu_init.tcl
psu_init
after 1000
psu_ps_pl_isolation_removal
after 1000
psu_ps_pl_reset_config
targets 9
rst -processor
dow test_a53/Debug/test_a53.elf
bpadd -addr &main

========================================================================================================

I have also tried to run the example design in xilinx-zcu111-v2018.3-final and when the linux is booting up the boot sequence gets stuck at:

========================================================================================================

[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.14.0-xilinx-v2018.3 (oe-user@oe-host) (gcc version 7.3.0 (GCC)) #1 SMP Mon Mar 25 06:33:29 UTC 2019
[ 0.000000] Boot CPU: AArch64 Processor [410fd034]
[ 0.000000] Machine model: ZynqMP ZCU111 RevA
[ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')
[ 0.000000] bootconsole [cdns0] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 256 MiB at 0x000000006fc00000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] percpu: Embedded 21 pages/cpu @ffffffc87ff61000 s46488 r8192 d31336 u86016
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: enabling workaround for ARM erratum 845719
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1033987
[ 0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.000000] software IO TLB [mem 0x6bc00000-0x6fc00000] (64MB) mapped at [ffffffc06bc00000-ffffffc06fbfffff]
[ 0.000000] Memory: 3777568K/4193280K available (10108K kernel code, 664K rwdata, 3224K rodata, 512K init, 2167K bss, 153568K reserved, 262144K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] modules : 0xffffff8000000000 - 0xffffff8008000000 ( 128 MB)
[ 0.000000] vmalloc : 0xffffff8008000000 - 0xffffffbebfff0000 ( 250 GB)
[ 0.000000] .text : 0xffffff8008080000 - 0xffffff8008a60000 ( 10112 KB)
[ 0.000000] .rodata : 0xffffff8008a60000 - 0xffffff8008d90000 ( 3264 KB)
[ 0.000000] .init : 0xffffff8008d90000 - 0xffffff8008e10000 ( 512 KB)
[ 0.000000] .data : 0xffffff8008e10000 - 0xffffff8008eb6200 ( 665 KB)
[ 0.000000] .bss : 0xffffff8008eb6200 - 0xffffff80090d40b0 ( 2168 KB)
[ 0.000000] fixed : 0xffffffbefe7fd000 - 0xffffffbefec00000 ( 4108 KB)
[ 0.000000] PCI I/O : 0xffffffbefee00000 - 0xffffffbeffe00000 ( 16 MB)
[ 0.000000] vmemmap : 0xffffffbf00000000 - 0xffffffc000000000 ( 4 GB maximum)
[ 0.000000] 0xffffffbf00000000 - 0xffffffbf1dc00000 ( 476 MB actual)
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc880000000 ( 34816 MB)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU event tracing is enabled.
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] irq-xilinx: /amba_pl@0/interrupt-controller@a00c2000: num_irq=2, edge=0x3

========================================================================================================

This seem to indicate that the PL - PS communication is blocking somehow and I am wondering if anyone has seen this issue with the ZCU111 development board. I have tried this with 3 boards and all of them demonstrate the same behavior.

Is there any jumper settings or hardware setting that I need to do to get this working. If I were to install Linux I am able to get the boards to run Linux as I expect as long as I don't try to talk to the PL.

Please help.

Thanks and Best Regards,

 

Sanka Piyaratna

block_design_1.png
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8 Replies
Highlighted
Moderator
Moderator
1,141 Views
Registered: ‎09-12-2007

Re: PS - PL communication

For downloading the bitstream is it not

fpga -f filename.bit

Everything else looks fine. I have a wiki for auto creating the jtag boot script. There is an example given that you can reference

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/84444479/TCL+script+to+auto-generate+a+jtag+boot+script+based+on+HDF+file+for+Zynq+Ultrascale

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Adventurer
Adventurer
1,119 Views
Registered: ‎01-28-2008

Re: PS - PL communication

Hi @stephenm

Thanks a lot for your reply. 

I have updated the test.tcl script as you suggested together with the help from the reference link. Still my error message I get is the same. Also, I am not even able to get the example design created for ZCU111 running on my board as I discussed. Is there any significant differences as far as MPSoC is concerned for RFSoC as opposed to the EG part for example?

Thanks and Best Regards,

Sanka

 

test.tcl:

connect
targets -set -nocase -filter {name =~ "PSU"}
fpga -f ../octopus_top.runs/impl_1/octopus_drfm_top_zcu111.bit
source octopus_drfm_top_zcu111_hw_platform_1/psu_init.tcl
psu_init
after 1000
psu_post_config
after 1000
psu_ps_pl_reset_config
after 1000
psu_ps_pl_isolation_removal
targets -set -filter {name =~ "Cortex-A53 #0"}
rst -processor
dow test_a53/Debug/test_a53.elf
con
after 500
stop

 

Error Message:

xsdb% mrd -force 0x80000000
Memory read error at 0x80000000. Instruction transfer timeout
xsdb% Info: Cortex-A53 #0 (target 10) Running
xsdb% Info: Cortex-A53 #0 (target 10) Stopped at 0x0 (Cannot resume. Cannot read 'pc'. Cannot read 'r0'. Instruction transfer timeout)

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Highlighted
Moderator
Moderator
1,115 Views
Registered: ‎09-12-2007

Re: PS - PL communication

what is at the 0x80000000? how are these clocked? are you using the ps/pl clocks or the clock on the rfdc?

if using the clock on the rfdc ip, then you would need to make sure that the clocks are programmed correctly.

How did you generate the psu_init.tcl (ie from what HDF is this from?)

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Adventurer
Adventurer
1,113 Views
Registered: ‎01-28-2008

Re: PS - PL communication

Hi @stephenm 

axi_gpio_0 is located at 0x80000000 (as shown in the block design capture). pl_clk0 from Zynq MPSoC module is used to clock this. Once the design is compiled in Vivado 2018.3 I exported the hardware together with the bit file. Subsequently I used xsdk to create a hello_world app. This psu_init.tcl is from this hdf file . What am I doing wrong?

Thanks

Sanka

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Moderator
Moderator
1,086 Views
Registered: ‎09-12-2007

Re: PS - PL communication

Where did the HW design come from? I dont think there ar board configs for the zcu111 in Vivado yet?

 

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Adventurer
Adventurer
1,076 Views
Registered: ‎01-28-2008

Re: PS - PL communication

I am not sure if I am answering the right question. I believe you are asking how I obtain the board design files for Vivado and the BSP?

The board design for Vivado was downloaded from "https://www.xilinx.com/support/answers/71538.html" and ran the following commands with in Vivado tcl to add the board design onto the design suite.

set_param board.repoPaths <path to board files>
get_board_parts *zcu111*

I downloaded the BSP from https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-zcu111-v2018.3-final.bsp and I used BOOT.BIN and image.ub files from the "images/linux" directory. 

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Adventurer
Adventurer
1,021 Views
Registered: ‎01-28-2008

Re: PS - PL communication

I managed to get this working by moving to 2018.2 tools Vivado and Petalinux. I also had to move to M_AXI_HPM0_FPD instead of M_AXI_HPM0_LPD. I am not sure why this is? I haven't yet has chance to fully investigate why 2018.3 tools were not working properly. I noticed I had the same issue when I compiled the example design as described earlier. However, I am able to get the pre-built images working as expected.

Cheers,

Sanka

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Moderator
Moderator
1,011 Views
Registered: ‎07-31-2012

Re: PS - PL communication

Hi @cesanka ,

Refer to https://forums.xilinx.com/t5/Embedded-Development-Tools/sdk-execution-error-and-memory-write-error/td-p/734387.

It may help you.

Regards

Praveen


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