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timmaexd
Visitor
Visitor
6,270 Views
Registered: ‎07-01-2015

PS PLL precise PL frequency of 48 MHz

Hi all,

 

I need a PL clock frequency of 48 MHz as precisly as possible.

 

I know that I have to setup divisor in Vivado Zynq Clock Wizard and there is a difference between Requested and Actual Frequency.

 

After configuring the PS PLLs, I have measured the actual ouput frequenzy with an oscilloscope. The best result was provided by the DDR PLL (Input Frequency: 33.33 MHz; Multiplier: 32; Divisor: 22), whose frequency fluctuated around 48.5 MHz. But this deviation is too high.

 

Does anybody know how to get a output frequency of 48 MHz with the PS PLLs as precisly as possible?

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austin
Scholar
Scholar
6,267 Views
Registered: ‎02-27-2008

t,

 

Use something other than 33.33... MHz.  You are limited by the values of the M an D counters in the PS PLL.

 

Why do you need 48 MHz?  What are you tring to do?

 

And, precise means many things:  is it the frequency?  Or is it with little jitter?  And how precise? 1E-3, or 1E-15?  Could you calibrate it?  Do you have internet connectivity (you could use internet time protocol)?

 

You may use the PL to create a direct digital frequency synthesizer (DDFS) with arbitrary precision (48 bits is setps of 3.5E-15 of the frequency desired).  The input clock to the DDFS should be at least twice the output desired, an even better, 5X the desired output.

 

For example, the 33.33 gets used to create the AXI bus clock, whic is 100 MHz.  You can use a PL MMCM to create a 400 MHz clock, to drive a DDFS, to get 48 MHz, +/- 3.5E-15.

 

Is that precise enough?  Then you need to worry about how accurate the 33.33 MHz is (do you need an even more accurate 33.33 MHz?).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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gszakacs
Professor
Professor
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Registered: ‎08-14-2007

The ratio you want is 36/25.  Don't the M and D values go that high?

-- Gabor
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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

even a -1 zynq can support a VCO at 1200 MHz so 36/25 should definitely be possible.
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