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Explorer
Explorer
541 Views
Registered: ‎02-06-2018

PS to PL Clearing Interrupt Register

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Hi,

I'm experimenting with PL <-> PS interrupts and my simple design is in below. A counter counts to certain value and sets the interrupt and PS should handle it. This works fine. Now, I want PS to clear the interrupt through AXI communication. So there should be an interrupt register that is set by PL and reset by PS. I know a register cannot have two drivers. What is the best way to approach this?

Design.PNG

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Explorer
Explorer
441 Views
Registered: ‎02-06-2018
I did it by modifying AXI code generated by Xilinx. A mentor of mine taught it to me. It works fine and I think this is the best way. So basically you don't really touch any AXI register, you create a pulse when AXI Master wants to write to an specific AXI address. That pulse now can be used anywhere, including de-asserting the interrupt.

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Explorer
Explorer
442 Views
Registered: ‎02-06-2018
I did it by modifying AXI code generated by Xilinx. A mentor of mine taught it to me. It works fine and I think this is the best way. So basically you don't really touch any AXI register, you create a pulse when AXI Master wants to write to an specific AXI address. That pulse now can be used anywhere, including de-asserting the interrupt.

View solution in original post

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