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Anonymous
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Package pin delay considerations for Zynq PS DDR3 PCB routing

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Dear Xilinx

 

I've recently started designing with the Zynq xc7z020clg484, and I have a question regarding the PS DDR3 hard-IP controller. During PCB layout I've adhered to the following DDR3 trace routing guidelines:

 

  • UG933 Zynq-7000 PCB Design and Pin Planning Guide: Section "DDR Trace Length" on p 62
  • Micron TN-46-14: Hardware Tips for Point-to-Point System Design
  • Freescale AN3940: Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces

After completing my layout, I saw in UG933 a section called "Package Differences" which mentions the existence of signal delays between device silicon and package pads. I then generated a *.pkg file using 'partgen -v xc7z020clg484' to investigate the magnitudes of these internal package delays.

 

In Byte-Lane 0 for example I saw that some pins have differences in delays equating to more than 10 pico-seconds. This is bad considering the trace matching constraints of 10 ps for DQ/DM to DQS that is given in the above mentioned documents. It is even worse for the Address / Control signal groups which have to be matched to the DDR clock net. Differences of 60 ps have been noted between some control nets and clock, which is far from the 10 ps specified in UG933.

 

I plan to run my DDR3 design at 533 MHz (1066 MT/s). Also, prior to designing my own board I've been using the Zedboard developmennt kit. On their website it is mentioned that they skipped accounting for individual package pin delays. See their statement here:

 

http://www.zedboard.org/content/ddr3-routing-zedboard-rev-c

 

They also mention that people designing their own board should consider accounting for these delays on the PCB trace lengths.

 

My question is this: can the DDR controller be configured to absorb these package pin delays, OR do I have to manually extend / shorten trace lengths of individual pins on the PCB to compensate for these delays? Is there even a chance that I can ignore these delays as have been done with the Zedboard?

 

Thank you in advance.

 

Riaan

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Xilinx Employee
Xilinx Employee
16,651 Views
Registered: ‎01-03-2008

Your PCB should compensate for the internal package delays to provide the most margin to interface.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

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Xilinx Employee
Xilinx Employee
16,652 Views
Registered: ‎01-03-2008

Your PCB should compensate for the internal package delays to provide the most margin to interface.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

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12,030 Views
Registered: ‎01-08-2012

Another thing to consider is that if you are using "package migration" - that is, if you intend putting different (but still supposedly pin compatible) devices on the same footprint, the package delay will not be the same on all the devices.

 

You can trim the lengths on the PCB to suit one device, but not all at once.

 

You can compare the package delays between the two (or more) parts in a spreadsheet and avoid the pins that have the most variation.

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Anonymous
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Thankyou very much for your help. I will compensate on the PCB.

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10,583 Views
Registered: ‎01-28-2015

Dear Xlinix:

Do you have package delay file for the xc7z020clg400?

I tried to use the write_csv command with the Vivido but see error messaeg:

write_csv pindelay.csv
ERROR: [Common 17-53] User Exception: No open design. Please open a design before executing this command.

 

Please advice ASAP

thanks

 

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10,582 Views
Registered: ‎01-28-2015
 
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Xilinx Employee
Xilinx Employee
10,567 Views
Registered: ‎02-06-2013

Hi

 

As mentioned in the error you need to have a opened elaborated, synthesized or implemented design in vivado before using the command to write the csv file.

Regards,

Satish

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Observer
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Registered: ‎02-22-2015

Hello,

 

We are in a silimilar situation: finishing our schematic and gathering information to begin to design our layout.

I have generated the package file for xc7z010clg400-1 but what I really worry is that Xilinx also suggest to take into account memory package and unfortunately I can't find any datasheet of DDR3 manufacturers (Micron, ISSI, Alliance,..) talking about internal pin delays.

 

Can someone give us a hint?

 

Thank you.
Manuel.

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Visitor
Visitor
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Registered: ‎11-17-2014

How do I get the package delays for the Zynq PS DDR interface.   I've been looking for the information for some time.

 

I've heard that there is a package delay file, but that it is more accurate to extract the package delays from the IBIS model.

 

Which is better, the package delay file (and how is it generated), or using the ADEPT program to extract the RLC data from the bottom of the IBIS model ?

 

Thanks,

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8,110 Views
Registered: ‎01-08-2012

@donowilk wrote:

How do I get the package delays for the Zynq PS DDR interface.   I've been looking for the information for some time.

 

I've heard that there is a package delay file, but that it is more accurate to extract the package delays from the IBIS model.

 

Which is better, the package delay file (and how is it generated), or using the ADEPT program to extract the RLC data from the bottom of the IBIS model ?

 

Thanks,


 

This thread may have the answer to your "how is it generated" question:

https://forums.xilinx.com/t5/7-Series-FPGAs/Zynq-chip-bond-lengths/m-p/668797

Regards,

Allan

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