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chadjerde
Adventurer
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Registered: ‎08-27-2013

Partial Reconfiguration of PCIe Block on Zynq-7000

I have a design that uses the PCIe block as a root port in certain modes.  Though critical, it is rarely used.  I am noticing that I have 2W constant power draw with a PCIe block in my design.  I have been looking into partial reconfiguration to see whether it would be possible to only enable the PCIe block when needed.  Is this possible.

 

My reading of UG909 (v2016.3) pg 13. makes me think this may not be possible but would if I were using an Ultrascale device. Is this the case?

 

Any other suggestions on how I might avoid this continual power draw when I am not using the PCIe functionality of the design?

 

 

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chadjerde
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Registered: ‎08-27-2013

I am still trying to figure out whether it is possible to use partial reconfiguration of the pcie_express on the zynq-7000.  ug909 pg. 12 under the heading "Design Criteria" led me to believe that it was not possible to do this since the PCIe is only listed as being a reconfigurable component for UltraScale devices.  Though on pg. 58 under 
"Design Elements Inside Reconfigurable Modules" PCIe is listed as logic that can be placed in a reconfigurable module for 7 series devies. 

 

Does anyone have any insight into how to go about doing this?

 

Thank you.

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chadjerde
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Registered: ‎08-27-2013

Drawing attention to this post.  Is it possible to dynamically reconfigure the PCIe core on a zynq-7000 device?

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