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davej56332
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Registered: ‎10-17-2014

Partial Reconfiguration problems with AXI HWICAP for ZYNQ 7000

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Hello,

 

I've been working on a PR design using the AXI HWICAP IP on a zc706 board and need some help...

I've added the AXI HWICAP IP to my hardware design, connected it to the PS section via AXI4 Lite and now I'm trying to interface with it in a bare metal application using the drivers provided in the BSP. I've ensured RESET_AFTER_RECONFIG is enabled in the hardware design, I've disabled the pcap in software via XDcfg_DisablePCAP(), and I've enabled the ICAP interface via XDcfg_SelectIcapInterface(). When I go to write my bitstream to the ICAP via XHwIcap_DeviceWrite(), it return successful but doesn't configure anything! After calling the DeviceWrite function, the ICAP status register reads 0x7 which states that the ICAP is in a hung state according to DS817. Also, IP interrupt status register reads 0x5 which states that the write FIFO is empty. All other registers read 0x0.

 

What could I be doing wrong here? I've converted the partial .bit file to a .bin file via promgen with the -p bin flag and I'm using that. Is my bitstream bad? What can cause the ICAP hung bit to be set? I'm using ISE 14.7 btw. If anyone can help that would be greatly appreciated. I've been going mad trying to figure this out.

 

Thanks

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davej56332
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I was able to get it working! The deltas from what I was doing before are given below...

 

Created a new project and followed my flow from start to finish for this entirely new project.

When adding the AXI_HWICAP, I drove the ICAP_Clk with a separate 100MHz clock signal from the PS (before I was driving the ICAP_Clk with the same signal as the S_AXI_ACLK).

In SDK, used one standalone bsp for my software applications (I was using separate BSP for each application before)

Triple checked all of my settings along the way.

 

One, or a combination, of the things listed above did it for me. I interfaced with the AXI_HWICAP as I did in my other project and it worked the first try. If I had to guess on which one solved it, I would say it would be driving the clock with a separate signal. It probably caused some timing issues or something similar. Thank you so much for helping me out with this. You were great help with trying to debug this issue.

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austin
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dave,

 

I am unsure of what your sequence is here, but in Zynq as the processor system (the PS) controls everything at the start (the FSBL), in the beginning the PCAP is used to configure the FPGA device logic (fabric or PL).

 

Once the PS is running, as you state, your application needs to keep the PCAP, as that is how the processor will talk to the ICAP primitive if that is what you want to do.

 

Releasing the PCAP allows access to the ICAP from the PL using HWICAP (as you describe).

 

So, if you have partial bitstreams to load, you may do that through the PCAP (as booted, or later from PS to PL).

 

HWICAP is usually used with a MicroBlaze(tm) in the PL.  Of course you may interface with AXI bus from the PS to the PL, but do you really need to do that?  (more complexity than is required -- see below)

 

If you use the PS, there is no need for HWICAP (just send data through the PCAP).

 

http://www.xilinx.com/support/answers/46913.html

Austin Lesea
Principal Engineer
Xilinx San Jose
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davej56332
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Our application requires to use the ICAP for reconfiguration on bare metal, so unfortunately the complexity is required. I am able to do reconfiguration via DevC/PCAP with no problems. I'm trying to work out how to use the AXI_HWICAP pcore available from the IP Catalog in the Platform Studio. I'm referencing ds817 and it seems I am adhering to the spec, but it's not working.

 

I found this (http://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-ICAP-problem/m-p/317275/highlight/true#M8028) forum post that seems to be a very similar issue to what I am seeing, however, his solution was to attach it to the PS instead of a microblaze. My current configuration has the AXI_HWICAP connected to the PS, but I am still having problems. Is the ICAP hang status relevant?

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austin
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Figure 6.2 in ug585,

 

Shows the block view.

 

If you have a control program running on the ARM porocessors, and you wish to talk to the ICAP using the HWICAP in the fabric (PL) which is interfaced to the AXI bus, then the ICAP path is enabled, and the PCAP path is disabled (the mux needs to be selected to allow ICAP access to the configuration module).

 

ug702 recommends use of pcap for partial configuration.  So going that way is likely to be fully supported (as that is how we recommend doing it).  You may of course not go that way (as you are presently).

 

Nothing about using pcap is unique to Linux, nor bare metal, so with a baare metal system (no OS), you just need to create the software to drive the pcap.  Generally, working in c is far more efficient than working in RTL, so I still suggest you go with PCAP and write your own driver in c code, rather than write a driver (anyway) to go through to the AXI controller and ICAP instantiated in the PL.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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davej56332
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@austin wrote:
...the ICAP path is enabled, and the PCAP path is disabled (the mux needs to be selected to allow ICAP access to the configuration module)....

 


What does this look like in code? Is there any more to this than driving bit 27 of the DevConfig control register low?

I am doing this, so if there is nothing else, I'm not sure what else could be wrong.

 

If I could use PCAP I would, but it does not suit our needs for this application.

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austin
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OK,

 

Let me think about it.

 

Why must you use ICAP, and not PCAP?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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davej56332
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It does not satisfy our requirements

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austin
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That is odd,

 

They both use ICAP, one from the PL, the other from the PS.

 

Is this a safety-critcal system application?  I could understand that, as it may have to do with partitioning, and single (common) points of failure.  But even then, the ICAP is common to both.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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wojciec
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http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

 

To make sure you've selected ICAP, please look at page 1134. I suggest you disable PCAP. This is actually 2 bits, not one:

 

- bit 27 PCAP_PR = 0

- bit 26 PCAP_MODE = 0

 

Let us know if it worked for you.

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austin
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And, from another expert here:

 

"

Austin, this is a lot like SEM IP use case in Zynq, where we need the ICAP to be functional.

After you load the bistream through PCAP, you need to set the PCAP_PR bit to allow ICAP access to the config logic.  By doing this, the PCAP becomes unresponsive until the time you change the PCAP_PR setting back to the original value.

With SEM IP core, we have to send it a signal when it's free to use ICAP, because by default it thinks it owns ICAP and just starts...  Maybe the ICAP controller in this guy's design is making the same assumption, and because initially ICAP is not responding, it locks up?"
Austin Lesea
Principal Engineer
Xilinx San Jose
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davej56332
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I was able to get it working! The deltas from what I was doing before are given below...

 

Created a new project and followed my flow from start to finish for this entirely new project.

When adding the AXI_HWICAP, I drove the ICAP_Clk with a separate 100MHz clock signal from the PS (before I was driving the ICAP_Clk with the same signal as the S_AXI_ACLK).

In SDK, used one standalone bsp for my software applications (I was using separate BSP for each application before)

Triple checked all of my settings along the way.

 

One, or a combination, of the things listed above did it for me. I interfaced with the AXI_HWICAP as I did in my other project and it worked the first try. If I had to guess on which one solved it, I would say it would be driving the clock with a separate signal. It probably caused some timing issues or something similar. Thank you so much for helping me out with this. You were great help with trying to debug this issue.

View solution in original post

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chenfeng5009
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Registered: ‎05-08-2018

My project need to using hwicap ip core for partial reconfiguration. can you show me the code about hwicap devicer .

thanks

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chenfeng5009
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Registered: ‎05-08-2018

email:363466038@qq.com

thanks

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