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Observer
Observer
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Registered: ‎03-05-2019

Permanently Disable Microblaze Cache over Address Range

I have a single core Microblaze 10.0 system utilizing external DDR memory. I have a custom peripheral connected via DMA to the DDR memory. I am able to sucessfully write and read into memory with my custom peripheral. I have run into cache coherency issues where the Microblaze is sometimes not aware of the updates made to DDR by my DMA peripheral.

I am aware that it is possible to invalidate/flush from software, but I would like to avoid this and the coresponding performance hit. I would also like to avoid ACE so I can continue to use write-back for the rest of the cache. Is it possible to permanetly disable caching an address range with the microblaze to force it to read from DDR every time when reading from a particular address range? It appears that this is possible for the Zynq. This data range may be allocated at build time.

I tried setting the "high address" of the data cache to include only the lower half of DDR memory, but attempts to read from the upper (unchached) portion of memory from microblaze returned a constant value of 0xDEC0DE1C.

Thanks in advance for any help.

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Participant
Participant
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Registered: ‎06-27-2019

I have the same question.

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