cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
vapham
Contributor
Contributor
837 Views
Registered: ‎06-02-2019

Pin assignment for fmcp hspc ZCU111

Jump to solution

Hello everyone,

I tried to use SPI in Ultrascale RFSoC and set SPI0 to EMIO. I attached the screenshot showing part of the connection.

vapham_0-1603877212543.png

I assigned the output of SPI to J26 of card ZCU111 (FMCP HSPC connector) as follow:

set_property PACKAGE_PIN AJ13 [get_ports {emio_spi0_m_i_0}]      # MISO
set_property PACKAGE_PIN AH13 [get_ports {emio_spi0_sclk_o_0}]	 # CLK
set_property PACKAGE_PIN AH12 [get_ports {emio_spi0_m_o_0}]      # MOSI
set_property PACKAGE_PIN AG12 [get_ports {emio_spi0_ss_o_n_0}]	 # SS
  
set_property IOSTANDARD LVCMOS33 [get_ports {emio_spi0_m_i_0}]
set_property IOSTANDARD LVCMOS33 [get_ports {emio_spi0_sclk_o_0}]
set_property IOSTANDARD LVCMOS33 [get_ports {emio_spi0_m_o_0}]
set_property IOSTANDARD LVCMOS33 [get_ports {emio_spi0_ss_o_n_0}]

 

But I got this error:

[DRC BIVB-1] Bank IO standard Support: Bank 65 has incompatible IO(s) because: The LVCMOS33 I/O standard is not supported for banks of type High Performance. Move the following ports or change their properties:
emio_spi0_m_i_0

Is it possible to set emio_spi0_m_i_0 at LVCMOS33?

Thank you

0 Kudos
1 Solution

Accepted Solutions
barriet
Xilinx Employee
Xilinx Employee
764 Views
Registered: ‎08-13-2007

Bank 65 as indicated by the error message is HP I/O.

See https://www.xilinx.com/support/documentation/user_guides/ug1075-zynq-ultrascale-pkg-pinout.pdf page 74 for v1.9

HP (high performance) I/O is optimized for LVDS, DDRx, and MIPI - it does not support voltages above 1.8V. see https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

The error message is correct - you can't assign LVCMOS33 here. There's also the related but different issue of the Vcco for the respective bank on the development board.

It is possible you could interface a LVCMOS18 output from the ZU28DR to an LVCMOS33 input on another circuit - but you'll need to watch the specs like Voh (RFSoC) and Vih (external device) - and be considerate of noise margin, etc.

Cheers,

bt

View solution in original post

6 Replies
venui
Moderator
Moderator
776 Views
Registered: ‎04-09-2019

Hi,

Yes, it is possible to connect to LVCOM33 but the EMIO pins which you choose should be compatible with the voltage level other wise you will get the same errors, so i would like to request you to cross verify the voltage level supported by particular bank and change the the pin constrains as per the requirements.

Regards,

Venu 

barriet
Xilinx Employee
Xilinx Employee
765 Views
Registered: ‎08-13-2007

Bank 65 as indicated by the error message is HP I/O.

See https://www.xilinx.com/support/documentation/user_guides/ug1075-zynq-ultrascale-pkg-pinout.pdf page 74 for v1.9

HP (high performance) I/O is optimized for LVDS, DDRx, and MIPI - it does not support voltages above 1.8V. see https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

The error message is correct - you can't assign LVCMOS33 here. There's also the related but different issue of the Vcco for the respective bank on the development board.

It is possible you could interface a LVCMOS18 output from the ZU28DR to an LVCMOS33 input on another circuit - but you'll need to watch the specs like Voh (RFSoC) and Vih (external device) - and be considerate of noise margin, etc.

Cheers,

bt

View solution in original post

vapham
Contributor
Contributor
732 Views
Registered: ‎06-02-2019

Thank you for your reply,

Do you have any example or the reference on the interface LVCMOS18 - LVCMOS33 on another circuit?

Regards

0 Kudos
barriet
Xilinx Employee
Xilinx Employee
712 Views
Registered: ‎08-13-2007

I've had at least one customer use a Texas Instruments level translator/buffer to interface from Virtex-7 HP (also limited to 1.8V) I/O to external 3.3V legacy circuits - but don't have the part # immediately handy.

Other considerations include:

-you need to be aware of the potential timing impact here given the additional external propagation delays.

-bidirectional circuits can have additional considerations (which doesn't sound like the case here) since you have to control the FPGA/MPSoC output enable and the external buffer direction as well

vapham
Contributor
Contributor
703 Views
Registered: ‎06-02-2019

Thanks bro for the very useful information

0 Kudos
barriet
Xilinx Employee
Xilinx Employee
697 Views
Registered: ‎08-13-2007

Glad to help.

I checked my notes - it was a SN74AVC32T245 - though it was for a DSP EMIF interface, not a SPI interface.

Here's some other related resources you might find useful:

http://www.xilinx.com/support/documentation/application_notes/xapp520_7Series_HPIO.pdf (Interfacing 7 Series FPGAs High-Performance I/O Banks with 2.5V and 3.3V I/O Standards)
https://www.xilinx.com/support/documentation/application_notes/xapp899.pdf (Interfacing Virtex-6 FPGAs with 3.3V I/O Standards)
https://www.xilinx.com/support/documentation/application_notes/xapp646.pdf (Connecting Devices in the Virtex and Spartan Families to a 3.3V or 5V PCI Bus)
https://www.xilinx.com/support/documentation/application_notes/xapp785.pdf (Level Translation Using Xilinx CoolRunner-II CPLDs)

As you can see, the problem has been around for awhile - and the approach can be different depending on the device, application, situation, etc.

Cheers,

bt

0 Kudos