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Contributor
Contributor
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Registered: ‎08-22-2007

Place:872 - Delay element

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I am trying to build a small project with a FX70 FPGA on a custom board, using EDK 11.2. I have a project based on the ML507 dev kit with a PPC, bram memory and a TEMAC using the hard MAC. I have then changed the ucf file to match the pin map of my custom board and I have changed the IDELAY_CTRL loc constraints in the config dialog for TEMAC (everything else is as for the ml507 board). When trying to implement the design I get the following error:

 

 ERROR:Place:872 - Delay element
   "Hard_Ethernet_MAC/Hard_Ethernet_MAC/V5HARD_SYS.I_TEMAC/SINGLE_GMII.I_EMAC_TO
   P/gmii0/YES_IO_1.ideld5" has been placed at IODELAY_X2Y189 due to the
   following location constraint on component
   "fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<5>":
       COMP "fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<5>" LOCATE =  SITE "P7" LEVEL
   1
   However, the delay controller that calibrates this delay element has not been
   used. Please instantiate a delay controller and apply appropriate location
   constraint, or instantiate one delay controller for the design with out any
   location constraint. Please refer to the usage document to use the controller
   efficiently.

 

If I understand thing correctly, the P7 pin should use the IDELAY_CTRL at X1Y4, which is one of the loc constraints in the TEMAC dialog. The error messge repeats for several signals, all corresponding to the two sites that I have loc:ed.

 

Any theories on this?

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Xilinx Employee
Xilinx Employee
6,252 Views
Registered: ‎08-13-2007

Re: Place:872 - Delay element

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You don't mention which package (FF665 or FF1136) you're using. But assuming that it is the FF1136 like the ML507, the associated IDELAYCTRL for P7 is IDELAYCTRL_X2Y4.

 

 

die view generated by ADEPT:

http://mysite.verizon.net/jimwu88/adept/

 

Cheers,

bt

 

BTW, this question is likely better suited for the Virtex board since it isn't Embedded Processing-specific.

 

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Xilinx Employee
Xilinx Employee
6,253 Views
Registered: ‎08-13-2007

Re: Place:872 - Delay element

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You don't mention which package (FF665 or FF1136) you're using. But assuming that it is the FF1136 like the ML507, the associated IDELAYCTRL for P7 is IDELAYCTRL_X2Y4.

 

 

die view generated by ADEPT:

http://mysite.verizon.net/jimwu88/adept/

 

Cheers,

bt

 

BTW, this question is likely better suited for the Virtex board since it isn't Embedded Processing-specific.

 

View solution in original post

temp.JPG
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Contributor
Contributor
5,204 Views
Registered: ‎08-22-2007

Re: Place:872 - Delay element

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Thanks for the help. I will try to explore IDELAYCTRL locations with Adapt which was available for download today, unlike yesterday, and post my progress. However I still don't have any idea on the fundamental issue: Which pins need IDELAYCTRL elements? There is nothing specific in the IP datasheet and I haven't found anything anywhere else.

 

Regards

Johan

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

Re: Place:872 - Delay element

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The IDELAYCTRL is described in the User Guide and Libraries Guide.

Here's another useful app note even though it was originally written for V4:

http://www.xilinx.com/support/documentation/application_notes/xapp707.pdf (Advanced ChipSync Applications)

 

There has been some changes on how the IDELAYCTRL was handled (e.g. replication in map) between ISE releases and from V4 to V5. The basic rule I use  is: you need an IDELAYCTRL for every bank that has I/O configured to use the IDELAY (V4) or IODELAY (V5). I find that ADEPT's color coding of the I/O regions and optional display of the IDELAYCTRL (View -> Display IDELAYCTRL) to be helpful here. The ability of ADEPT to read in an ncd can also be useful at times.

 

http://www.xilinx.com/support/answers/24704.htm (Virtex-5, Virtex-4 - IDELAYCTRL location)

http://forums.xilinx.com/xlnx/board/message?board.id=EDK&message.id=4757 (How to give IDELAYCTRL in EDK)

http://www.xilinx.com/support/answers/25051.htm (9.1i Virtex-5 PAR - What are the rules for IDELAYCTRL replication and optimization?)

 

bt

 

 

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