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hsuh6
Visitor
Visitor

‎01-08-2021 09:07 PM - edited ‎01-08-2021 09:09 PM

250 Views
Registered: ‎04-28-2020

Possible bug in AXI clock converter IP example file.

Hi, 

While I am working on the AXI clock converter, I wanted to see the example project of it because that example project helped me a lot in my previous project with CDMA IP.

However, it give me an error like below

AXI clk converter question to Xilinx.PNG

This error is from Vivado 2020.1 and I am using ZCU102 board as a testbed. Is it not supported for this board by any chance?

I also have tried opening the same IP example in Vivado 2019.2, but without any luck.

It gave me exactly the same messages and errors as given in the screenshot.

 

Best,

Hsuh6

AXI clk converter question to Xilinx.PNG
Reply
1 Reply
abouassi
Moderator
Moderator

‎02-05-2021 03:05 AM

106 Views
Registered: ‎03-25-2019

Hi @hsuh6,

Thanks for reporting that.
I was able to reproduce that and I have reported that locally to be fixed.

Best regards,
Abdallah
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