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Explorer
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Registered: ‎05-21-2009

PowerPC 440 cache problem

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Good day.

 

I have a question regarding PowerPC 440 cache. I have a system running a state machine. In order to change states, I have a simple interrupt triggering a flag to indicate a state change. My main loop continues to run, intil the interrupt flag is set. To improve system performance, I have enabled (or tried to enable) instruction and data cache by using XCache_EnableICache and XCache_EnableDCache.

 

I have DDR memory at location 0x000000000 to 0x0FFFFFFF and BRAM at 0xFFFF0000 to 0xFFFFFFFF, so I decided to use:

 

XCache_EnableDCache(0x80000000) to cache the data to the DDR, and XCache_EnableICache(0x00000001) to cache the instructions to the BRAM.

 

This improved system performance a lot. However, I am unable to change states. If I play around with the addresses of the two "Enable"-functions, I am able to change states only once.

 

Now, am I interpreting the two memory addresses of the functions correctly that this is where I cache to, secondly, what could be the reason for not being able to change states? Should I flush or clear the cache to be able to receive new data? And thirdly, should I make any changes to the PowerPC hardware to be able to use cache (I am using EDK 11)?

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Explorer
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Registered: ‎05-21-2009

Hi, thanks for your replies.

 

I found a solution. The problem was the way I was using the cache. I misunderstood XCache_EnableICache and XCache_EnableDCache functions. The "regions" parameter states the memory that should be cached, not the memory to where it should cache.

 

The way I understand it is as follows: The state machine uses a variable in the DDR to change states. On the first execution, the DDR is cached and the state changes, since the new parameter is cached. However when the next interrupt triggers, the old value is still in the cache. The cache should first be invalidated before the new parameter is cached. (Can anyone confirm that this is indeed what is happening?)

 

So here's my solution: I ensured I was caching the right region, thus sending the correct parameter to XCache_EnableICache and XCache_EnableDCache. And then to invalidate the cache before using it. 

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Registered: ‎08-29-2008

Hi,

 

I am wondering about the issue that you are not able to change states! The cache is completely transparent!

It doesn't matter whether the states remain in cache or not! Does the FSM use only DDR-RAM or BRAM or

both in the same scope?

 

Rgds,

Kai

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7,843 Views
Registered: ‎05-01-2009

check ppc440_0/libsrc/standalone_v2_00_a/src/xcache_l.c

 

XCache_EnableDCache(0x80000001); 

 

we have 32bit, an 1 bit is means 256Mbyte, so using 0x8000001 is ok for you. 

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9,843 Views
Registered: ‎05-21-2009

Hi, thanks for your replies.

 

I found a solution. The problem was the way I was using the cache. I misunderstood XCache_EnableICache and XCache_EnableDCache functions. The "regions" parameter states the memory that should be cached, not the memory to where it should cache.

 

The way I understand it is as follows: The state machine uses a variable in the DDR to change states. On the first execution, the DDR is cached and the state changes, since the new parameter is cached. However when the next interrupt triggers, the old value is still in the cache. The cache should first be invalidated before the new parameter is cached. (Can anyone confirm that this is indeed what is happening?)

 

So here's my solution: I ensured I was caching the right region, thus sending the correct parameter to XCache_EnableICache and XCache_EnableDCache. And then to invalidate the cache before using it. 

View solution in original post

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Contributor
Contributor
7,837 Views
Registered: ‎05-01-2009

why you just put the valule in to a noncache memory. you can split you memory layout to two part, for example one part 256Mbyte, other part is 32Mbyte

you can using Xcache_enableCache making the 256Mbyte as cached memory, and the 32Mbyte is non cached memory.

 

in linux we using ioremap_nocache doing the same thing.

 

hope it can help, thanks. 

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7,833 Views
Registered: ‎05-21-2009

Hi linuxbest.

 

Well, I'm not atually using any data from the DDR in my project except fot the state variable, so it is entirely possible to put the value in non-cache memory. In fact, I've disabled cache for the DDR, and then the program still works fine. I even get better performance since the PowerPC doesn't waste time invalidating the cache.

 

Thanks for your input.

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