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rikusleroux
Explorer
Explorer
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Registered: ‎05-21-2009

PowerPC/FPGA RAM interface problem

Hi. I'm getting a strange phenomenon and I was hoping someone could provide some insight to my problem.

 

Here's my setup: I'm using BRAM instantiated on a Virtex5-VFX FPGA to interface between the PowerPC 440 on the device and my VHDL code. The BRAM is intantiated using the language templates from Xilinx, thus:

 

type DP_RAM is array (0 to 2**16-1) of std_logic_vector (0 to 31); shared variable DualPort: DP_RAM; begin -------------------- -- Port A process -- -------------------- Port_A: process (CLK_A) begin if (CLK_A'event and CLK_A = '1') then if (CE_A = '1') then if (WE_A = '1') then DualPort(conv_integer(unsigned(ADD_A))) := DIN_A; end if; DOUT_A <= DualPort(conv_integer(unsigned(ADD_A))); end if; end if; end process; -------------------- -- Port B process -- -------------------- Port_B: process (CLK_B) begin if (CLK_B'event and CLK_B = '1') then if (CE_B = '1') then if (WE_B = '1') then DualPort(conv_integer(unsigned(ADD_B))) := DIN_B; end if; DOUT_B <= DualPort(conv_integer(unsigned(ADD_B))); end if; end if; end process;

 

with both address A and B 32 bit values. The data is also 32 bits, but the size of the ram is (as can be seen from the DP_RAM array) is 65536.

 

To interface the BRAM from the PowerPC, I'm using the XPS BRAM memory controller. The test code I have written fills the BRAM from the FPGA connected to port B with values 0 at position 0, 1 at position 1 and so forth. The code is as follows:

 

 

write_memory: process(CLK) begin if (RESET = '1') then WE_B <= '0' ; CE_B <= '0' ; add_counter <= 0 ; -- Used to increment addresses sec_counter <= 0 ; -- Second counter as a delay to write to memory elsif (CLK'event and CLK = '1') then if ((add_counter < 65536) and (sec_counter < 133_000_000)) then sec_counter <= sec_counter + 1 ; WE_B <= '0' ; CE_B <= '0' ; memory_int <= "0" ; -- used to trigger interrupt on PowerPC elsif ((add_counter < 65536) and (sec_counter >= 133_000_000)) then WE_B <= '1'; CE_B <= '1' ; ADD_B <= conv_std_logic_vector(add_counter,32) ; DIN_B <= conv_std_logic_vector(data_counter,32) ; add_counter <= add_counter + 4 ; -- Initialstatement was add_counter <= add_counter + 1 data_counter <= data_counter + 1 ; sec_counter <= 0 ; memory_int <= "1" ; else WE_B <= (others => '0') ; CE_B <= '0' ; end if ; end if ; end process write_memory ;

 

 

The PowerPC then reads the values and displays them in Hyperterminal.

 

Now, when the code on the PowerPC is run, only every fourth value is shown. When viewing the memory map, the BRAM starts at location 0x00000000 (as specified)which holds the value 0x00000000 (which is correct), and since I write 32 bit values to RAM, the next value (0x00000004) is at location 0x00000004. This implies that to get the second value, which should be 0x00000001 at the second memory location (0x00000004), I should write the second value (from the FPGA) at the fourth position in DP_RAM (see add_counter + 4 in above code), why is this? This does not make sence when viewing the VHDL code, since each position in DP_RAM holds a 32 bit value, thus should the second value be at position 2.

 

Can anyone give me more insight on this? I hope my description is clear.

 

Thanks

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code_slave
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Registered: ‎01-04-2009

Hi,

Do you have the full project, or can you make it available?

 

Steve

 

 

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rikusleroux
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5,246 Views
Registered: ‎05-21-2009

Hi Steve

 

Thanks for your interest in finding a solution to my problem. I spoke to a few people about this occurance, and apparently it is quite common when addressing RAM instantiated on an FPGA and accessing it via a PowerPC.

 

The best solution I found was scaling the PowerPC address line where it is mapped to the dual port ram so that every fourth address points to a consecutive address in the dual port Ram.

 

Thanks for your interest!

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bassman59
Historian
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5,236 Views
Registered: ‎02-25-2008


rikusleroux wrote:

Hi Steve

 

Thanks for your interest in finding a solution to my problem. I spoke to a few people about this occurance, and apparently it is quite common when addressing RAM instantiated on an FPGA and accessing it via a PowerPC.

 

The best solution I found was scaling the PowerPC address line where it is mapped to the dual port ram so that every fourth address points to a consecutive address in the dual port Ram.

 

Thanks for your interest!


Yes, that makes sense -- the two least-significant processor address bits don't connect to anything, and you use the byte-lane enables to deal with non-32-bit writes.

 

-a

----------------------------Yes, I do this for a living.
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