I want to share a problem that I solved but that made me crazy! Maybe someone from Xilinx can explain if its normal or not and why.
Description of the initial problem:
I am using a ZCU106 evaluation board. I've created a Vivado 2020.1 project targeting the ZCU106 board. In a fist time I've implemented a very simple project with only a MPSOC system. A Petalinux distribution is running on it and all was Ok: in particular Ethernet3 on phy and UART0 for debug.
In a second time my need was to use a direct SGMII ethernet interface through SMA connectors and remap the PS UART1 to anothers IOs in the PL.
To do that I changed GEM3 and UART1 configuration in the MPSOC to connect it to EMIO in place of ZCU106 MIO.
I made all the necessary to connect those two interfaces through the PL.
All seems to be ok, but there was no signal on the new ethernet and UART. Moreover the UART was always connected and accessible by the FTDI chip.
It seams that the ZCU106 configuration overwrites the modification I made in the MPSOC.
I have no memory of such thing on ZC706 for example.
To work around this problem I changed the target from ZCU106 to the Zynq chip of the board.
And without changing anything in my design the two interfaces are working !
I've made tests with Petalinux and in Bare Metal and it was the same: The initial configuration of the ZCU106 MPSOC can't be changed.