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soto1980
Contributor
Contributor
4,623 Views
Registered: ‎04-25-2012

Problem in access DDR from PL with AXI bus (HP0) when modification is made in Boot Flow ZYNQ.

Axi_bug.png

 

 

 

Note:

Configuration HP0. Data Bus size: 32 bits

Configuration HP1. Data Bus size: 64 bits

                                       

Stage 1

Boot Flow:  BootROM -> FSBL (bitstream for the programmable logic) -> uBoot -> Image Linux

Everything works fine. Block A and B write in DDR3 and uC read from DDR3 correctly.

 

Stage 2

Boot Flow:  BootROM -> FSBL (WITHOUT bitstream for the programmable logic) -> uBoot -> bitstream for the programmable logic -> uBoot ->Image Linux

Note: uBoot know the position of bitstream inside flash

Block A (HP0) is not working fine, Block B work fine.

Analyzing behavior Block A with hardware manager seems to work fine. Signals on bus AXI are toggling correctly, but data is been writing in DDR3 have always zero value.  

 

Stage 3

Keep data flow of stage 2:

Boot Flow:  BootROM -> FSBL (WITHOUT bitstream for the programmable logic) -> uBoot -> bitstream for the programmable logic -> uBoot ->Image Linux.

Change configuration HP0, data bus size move from 32 to 64 bits.

Everything works fine. Block A and B write in DDR3 and uC read from DDR3 correctly.

 

Stage 4

Return to data flow of stage 1:

Boot Flow:  BootROM -> FSBL (bitstream for the programmable logic) -> uBoot -> Image Linux

Keep configuration HP of stage 3:

 Configuration HP0. Data Bus size: 64 bits

Configuration HP1. Data Bus size: 64 bits

Block A (HP0) is not working fine, Block B work fine.

Analyzing behavior Block A with hardware manager seems to work fine. Signals on bus AXI are toggling correctly, but data is not been writing in DDR3.  

 

Target: We need a HP configuration that support the both boot flow. Fsbl with and without bitstream. How can we achieve that?

 

Can you explain this strange behavior?

 

Thank in advance for help.

 

(Vivado version 2013.3)

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smarell
Community Manager
Community Manager
4,588 Views
Registered: ‎07-23-2012

Can you please share the logic debug screenshots during read/write transactions for test scenarios- 2/3&4?
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Registered: ‎05-29-2018

I see the same effect when configuring the FPGA from uboot.

Its like HP ports get configured wrongly.

Is there any Answer to this?

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Registered: ‎05-29-2018

Hello,
Can you help on this topic?
Thanks
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