02-08-2014 04:31 PM
I am new to create the custom peripheral IP on Zynq. I am trying to create a simple adder IP v12 in the custom peripheral template by vivado 2013.4 to the PS through AXI.
I successfully tested the PS to a custom_register template. Now I am trying to use three register inside the template as the input and output to the addsub IP v12. When using the IP packager, I can see the adder IP v12 is already included in the custom IP and it passes the P&R. However, when back to the embeded system block desigen, it always cannot pass the P&R with the black box error:
[Project 1-486] Could not resolve non-primitive black box cell 'c_addsub_0' instantiated as 'U0/register_adder_v1_0_S00_AXI_inst/regist_adder_0' ["h:/vivadoworkspace/customip/customip.srcs/sources_1/bd/zynq_1/ip/zynq_1_register_adder_0_0/hdl/register_adder_v1_0_S00_AXI.vhd":414]
I guess it means the new created addsub v12 IP is not successfully included to this embedded project. Does anyone can tell me how to solve it please?
02-09-2014 02:13 AM
Forgot the pics.
In the IP packager, the addsub IP is already included in the given custom IP template and can be sucessfully synthesis and P&R.
However, when back to the block design, the P&R shows a blackbox error: "[opt 31-30] The specified blackbox is not found in the existing library"
I read some solution for XPS, but it seems do not working for vivado. Why the addsub IP is not included in the library? How can I include the addsub IP into the block design?
02-09-2014 10:54 PM
From the error log, it seems the IP is not correctly recognized.Did it package it back to IP catalog?
Please check the
02-10-2014 02:24 AM
Thanks for the reply!
Yes, I have packed it to the IP catalog.
I have found AR#57128 about using xilinx IP core for custom peripheral.
It says the blackbox critical warning will appear since all the latest IP core are encrypted.
I also follow the suggestiong in AR#56644 by regenerating the output product with verilog.
However, it still does not work.
Since I have successfully synthesis and P&R my custom IP in the IP editor, I am sure I have successfully instanitiated the addsub v12 IP in the custom register peripheral IP template. But when back to the embedded block design, the error accurs like the encrypted addsub v12 IP is not readable by the vivado.
I also tried using the manual adder code and instanitiated it in the custom register peripheral IP template. There is no such error. So is that means we cann't using the encrypted xilinx IP core to build custom perihperal IP core by instanitiating it in the custom register peripheral IP template? Or are there anything else I missed here?
03-07-2014 07:53 AM
I have the same problem.
In XPS one needed to "name" balck box devices in the bbd file and put it into the same location as the pao-file.
Is there a similar mechnismen for Vivado ( I haven't found any pao o bbd-files to my regret ...)
05-20-2014 10:34 PM
Same problem here:
Did you solve it ??
I think one has to add the netlist .dcp to the package using
Package IP -> IP File Groups
But to which group should we add it?
Living was easier with ISE/XPS ...
05-21-2014 04:11 AM
Thanks for this update. Unfortunately, I have not solved the problem of using xilinx ip for custom peripheral. Instead, I use my own hand writing vhdl ip at the moment. As I mentioned before, it works.
10-19-2015 12:14 PM - edited 10-19-2015 12:16 PM
I am also having this problem where I have a custom IP and the tool appears to recognize it, but will not build it. It shows up as an IP in my IP repository, I can properly add the IP to my block design, I do "Validate Design" and everything passes but I can't get through implementation... I get:
[Opt 31-30] Blackbox arm_ps/arm_ps_block_i/axi_pattern_gen_0/U0 is driving pin IO of ... This blackbox canont be found in the existing library.
I've been through the IP Packager and made sure everything was up to date and then repackaged.
I've tried Tools -> Report IP -> Upgrade everything.
I've tried "Reset Output Products" and "Generate Output Products" and that works fine
I'm using 2015.2
I verified that my HDL does NOT have the "ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;" lines as mentioned in the previous posts. What else could be going wrong?