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jasmine
Visitor
Visitor
411 Views
Registered: ‎10-09-2020

Problem on using ACP port and AXIS interface

Hello,

I am using Ultra96 v2 board (Zynq UltraScale+ MPSoC) and I am trying to create a simple design to test the data transfer between PL and L2 cache using the ACP port. I successfully run a simple example using ACP port and AXI interface following @kawazome's instructions (How-to-use-the-ACP-port-to-read-from-and-write-to-L2-cache ). However, if my input and output are hls::stream and I need to use AXI Stream interface, I failed to run the design.

I created a simple IP using HLS that reads 64 bits stream data, adds 15 and then writes to the output stream. The transferred data type is shown below. I also created my block design and ipynb file. The program ran well with the HP port. 

struct my_ap_axis {
    ap_uint<64> data;
    ap_uint<1> last;
    ap_uint<8> keep;
}

 

Then I tried the ACP port with the same IP. But after generating the bitstream, the program cannot run on the FPGA. I do not know the reasons... I have re-customized the PS and the DMA_AXI module and also add some connections. The block design and the configurations of some IPs are as follows.

Block designBlock designAXI_DMAAXI_DMAPSPSPSPS

 

Also, the ipynb code is as follows. The execution will get stuck in the 5th cell.

1.
import sys
import os
import math
import time
import numpy as np
import pynq
import ctypes

2.
overlay = pynq.Overlay('design_1.bit')
dma = overlay.axi_dma_0
xlnk = pynq.Xlnk()
nn_ctrl = overlay.test_0
print('got an accelerator!')

3.
NUM = 360*640*3
in_buffer = xlnk.cma_array(shape=(NUM, ), dtype=np.uint8, cacheable = 1)
out_buffer = xlnk.cma_array(shape=(NUM, ), dtype=np.uint8, cacheable = 1)

for i in range(NUM):
    in_buffer[i] = 11
    out_buffer[i] = 15

print('in: {}\nout: {}'.format(in_buffer, out_buffer))

4.
rails = pynq.get_rails()
 
#nn_ctrl.write(0x0, 0) # Reset
nn_ctrl.write(0x10, 1) 
nn_ctrl.write(0x0, 1) # Deassert reset
dma.sendchannel.transfer(in_buffer)
dma.recvchannel.transfer(out_buffer)
dma.sendchannel.wait()
dma.recvchannel.wait()
        
print('in: {}\nout: {}'.format(in_buffer, out_buffer))   

 

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2 Replies
jasmine
Visitor
Visitor
324 Views
Registered: ‎10-09-2020

So sad.. 

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kawazome
Adventurer
Adventurer
262 Views
Registered: ‎04-02-2014

As explained in How to use the ACP port to read from and write to L2 cache? , The AxCACHE and AxPROT signal values and the transfer length per transaction are important.

I'm not familiar with AXI DMA. But does AXI DMA support these limits?
In particular,

  • Can AXI DMA change the value of AxCACHE?
  • Can AXI DMA change the value of AxPROT?
  • Can AXI DMA dynamically limit the burst transfer length?

 

 

 

 

 

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