02-01-2015 06:58 PM
I am using the EVAL_AD7961_FMCZ board to read values from the ADC into the Zedboard. I got the ADC verilog driver file from the Analog Devices WIKI project that uses AD7961 that has the following interface:
input m_clk_i, // 100 MHz Clock, used for tiing
input fast_clk_i, // Maximum 300 MHz Clock, used for serial transfer
input reset_n_i, // Reset signal, active low
input [ 3:0] en_i, // Enable pins input
input d_pos_i, // Data In, Positive Pair
input d_neg_i, // Data In, Negative Pair
input dco_pos_i, // Echoed Clock In, Positive Pair
input dco_neg_i, // Echoed Clock In, Negative Pair
output [ 3:0] en_o, // Enable pins output
output cnv_pos_o, // Convert Out, Positive Pair
output cnv_neg_o, // Convert Out, Negative Pair
output clk_pos_o, // Clock Out, Positive Pair
output clk_neg_o, // Clock Out, Negative Pair
output data_rd_rdy_o, // Signals that new data is available
output [15:0] data_o // Read Data
So making use of the AXI4Lite I have designed a hardware that reads and latches the value of data_o when the data_rd_rdy_o goes high. I debugged the hardware using ILA and the output wasn't as expected.
The first signal is the data_o (only last 16bits) and the second signal is the data_rd_rdy_o. The third one is where I latch the value of data_o. The data output looks strange as
Looks like data keeps accumulating till the data_rd_rdy_o goes high but it suddenly accumulates to zero sometimes.
The data output value is always zero or 21 (hex) no matter what input I give to the board.
Could some one please point out what could have gone wrong?
Heres my hardware setup :
02-02-2015 08:36 AM
02-02-2015 05:38 PM
Actually I got it working somehow but there are glitches in the data when I input the signal through a signal generator. However if input a DC signal from DC power supply the ADC seems to work fine. In case of the signal generator, the data has noisy spikes but the spikes do not appears when a DC signal is applied through DC pwoer supply.
Following is the data output from the DC power supply (1v and 2v)
And following is the data acquired from a square wave from signal generator
The glitch is also seen in Vivado waveform using ILA
Any ideas why is this happening when both signals are applied in the same way.
02-02-2015 08:11 PM
Sorry I forgot that the data was in 16bit signed 2's complement format. But still there seems to be some form of glitch, I will report back with the correct waveform.
02-02-2015 08:48 PM
Apart from everything the signal from the DC power supply was being read correctly, however suddenly the read value dropped to half. I'm trying to find the fault but actually I did not change anything in the hardware or SDK source file.
Sudden drop to half
02-03-2015 11:24 PM
I changed the ADC board configuration to read single ended volts and that problem is cleared now but the output is showing some strange phenomena when applied a sine wave of 5kHz:
2. The sample rate should be 5Mhz but the number of samples in the 5kHz single wave is ~400 which makes it calculates to a sample rate of 2MHz.
3. Also when I tried to check the sample rate through Vivado hardware debugging using ILA, I found the duration between two data_rd_out signals to be 20ns which takes the sample rate to 50MHz.
What could I be doing wrong?